read_verilog ../mult_unsigned.v hierarchy -top mult_unsigned proc memory -nomap equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx memory opt -full # TODO #equiv_opt -run prove: -assert null miter -equiv -flatten -make_assert -make_outputs gold gate miter #sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter design -load postopt cd mult_unsigned #Vivado synthesizes 1 DSP48E1, 40 FDRE. select -assert-count 1 t:BUFG
select -assert-count 40 t:FDRE select -assert-count 1 t:DSP48E1 select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
