read_verilog ../asym_ram_tdp_read_first.v hierarchy -top asym_ram_tdp_read_first proc memory -nomap equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx memory opt -full # TODO #equiv_opt -run prove: -assert null miter -equiv -flatten -make_assert -make_outputs gold gate miter #sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter design -load postopt cd asym_ram_tdp_read_first stat #Vivado synthesizes 1 RAMB18E1. select -assert-count 1 t:$mem select -assert-count 2 t:LUT2 select -assert-none t:$mem t:LUT2 %% t:* %D
