Blame · architecture/scripts/synth_xilinx_fully_selected.ys · 20804cae1a105a98443100e69ce8a17c31048b20 · lvzhengyang / yosys-tests · GitLab

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synth_xilinx_fully_selected.ys 69 Bytes

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Add tests for error mesages for 'architecture' test group.

committed 5 years ago

read_verilog ../top.v
select dffe
synth_xilinx
write_verilog synth.v