Blame · simple/scripts/prep_flatten.ys · 16de246aff65ca45bc951e42dca302cd31a86809 · lvzhengyang / yosys-tests · GitLab

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Add new tests to simple,misc,architecture

committed 5 years ago

read_verilog ../top.v
prep -flatten
synth -top top
write_verilog synth.v