read_verilog ../dynpreaddmultadd.v hierarchy -top dynpreaddmultadd proc memory -nomap equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx memory opt -full # TODO #equiv_opt -run prove: -assert null miter -equiv -flatten -make_assert -make_outputs gold gate miter #sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter design -load postopt cd dynpreaddmultadd #Vivado synthesizes 1 DSP48E1. select -assert-count 1 t:BUFG select -assert-count 24 t:FDRE select -assert-count 1 t:DSP48E1 select -assert-count 8 t:LUT1 select -assert-count 17 t:LUT2 select -assert-count 25 t:LUT4 select -assert-count 16 t:MUXCY select -assert-count 18 t:XORCY select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT1 t:LUT2 t:LUT4 t:MUXCY t:XORCY %% t:* %D
