read_verilog ../bytewrite_ram_1b.v hierarchy -top bytewrite_ram_1b proc memory -nomap equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx memory opt -full # TODO #equiv_opt -run prove: -assert null miter -equiv -flatten -make_assert -make_outputs gold gate miter #sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter design -load postopt cd bytewrite_ram_1b stat #Vivado synthesizes 1 RAMB36E1. select -assert-count 1 t:BUFG select -assert-count 32 t:FDRE select -assert-count 32 t:LUT2 select -assert-count 32 t:RAM32X1D select -assert-none t:BUFG t:FDRE t:LUT2 t:RAM32X1D %% t:* %D
