write_btor_mem_s.ys

read_verilog -sv ../top.v
memory_collect
proc
write_btor -s btor.btor
design -reset
read_verilog  -sv ../top.v
synth -top top
design -reset
read_verilog -sv ../top.v
memory
synth
abc
write_btor -s btor3.btor
design -reset
read_verilog -sv ../top.v
memory
synth -top top
abc -g AND,XOR,NOR
write_btor -s btor4.btor
design -reset
read_verilog -sv ../top.v
memory
synth -top top
abc -g ANDNOT,ORNOT
write_btor -s btor5.btor
design -reset
read_verilog -sv ../top.v
memory
synth -top top
abc -g cmos3
write_btor -s btor6.btor
design -reset
read_verilog -sv ../top.v
memory
abc -g AOI4
synth -top top
write_btor -s btor7.btor
design -reset
read_verilog -sv ../top.v
memory
abc -g OAI4
synth -top top
write_btor -s btor8.btor
design -reset
read_verilog -sv ../top.v
memory
aigmap
proc
write_btor -s btor9.btor
synth -top top
write_btor  -v btor10.btor
design -reset
read_verilog  -sv ../top.v
synth -top top
write_verilog synth.v