read_verilog ../yosys_rocket/AsyncResetReg.v ../yosys_rocket/EICG_wrapper.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.behav_srams.v ../yosys_rocket/plusarg_reader.v ../yosys_rocket/SimDTM.v proc hierarchy -generate -check -simcheck -purge_lib -keep_positionals -keep_portwidths -nokeep_asserts -auto-top design -reset read_verilog ../top.v synth write_verilog synth.v
