Blame · backends/scripts/write_firrtl_mem_wr.ys · 0343b35f1be6b46d9bb0dbb031ea9a6f644c1232 · lvzhengyang / yosys-tests · GitLab

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Add new tests to backends and frontends; Fix some tests from reported issues 7be25b8c SergeyDegtyar committed 5 years ago	1 2 3	`read_verilog ../top.v proc memory_dff -nordff`
Add tests for error messages to 'backends' test group. 21ce1bed SergeyDegtyar committed 5 years ago	4	`memory_collect`
Add new tests to backends and frontends; Fix some tests from reported issues 7be25b8c SergeyDegtyar committed 5 years ago	5 6 7 8	`opt_reduce clean write_firrtl firrtl.firrtl write_verilog synth.v`