Name |
Last commit
|
Last update |
---|---|---|
.. | ||
SystemVerilog | ||
SystemVerilog.hs |
- general refactoring in decl parsing - restrict charge strength to trireg - require const vars to be initialized - forbid const net declarations - disallow run-on declarations in packages and classes
Name |
Last commit
|
Last update |
---|---|---|
.. | ||
SystemVerilog | Loading commit data... | |
SystemVerilog.hs | Loading commit data... |