src/Language/SystemVerilog · 1a170f41c2d3e48cf800ed3e039fd802df605029 · lvzhengyang / sv2v · GitLab

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allow for stray semicolons in module items; allow for multiple struct field… · 1a170f41
```
allow for stray semicolons in module items; allow for multiple struct field declarations on one line
```
Zachary Snow committed Mar 29, 2019
1a170f41

Name	Last commit	Last update
..
AST		Loading commit data...
Parser		Loading commit data...
AST.hs		Loading commit data...
Parser.hs		Loading commit data...