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lvzhengyang
sv2v
Commits
fe90c7bb
Commit
fe90c7bb
authored
Nov 04, 2023
by
Zachary Snow
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fix inline explicit struct casts
parent
04546639
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4 changed files
with
29 additions
and
2 deletions
+29
-2
CHANGELOG.md
+1
-0
src/Convert/Struct.hs
+5
-2
test/core/struct_pattern_cast.sv
+16
-0
test/core/struct_pattern_cast.v
+7
-0
No files found.
CHANGELOG.md
View file @
fe90c7bb
...
...
@@ -15,6 +15,7 @@
*
Fixed an issue that prevented parsing tasks and functions with
`inout`
ports
*
Fixed conflicting genvar names when inlining interfaces and modules that use
them; all genvars are now given a design-wide unique name
*
Fixed unconverted structs within explicit type casts
*
Fixed non-typenames (e.g., from packages or subsequent declarations)
improperly shadowing the names of
`struct`
pattern fields
*
Fixed failure to resolve typenames suffixed with dimensions in contexts
...
...
src/Convert/Struct.hs
View file @
fe90c7bb
...
...
@@ -495,8 +495,11 @@ convertSubExpr scopes (Call e args) =
(
retType
,
_
)
=
fallbackType
scopes
e
args'
=
convertCall
scopes
e
args
convertSubExpr
scopes
(
Cast
(
Left
t
)
e
)
=
(
t
,
Cast
(
Left
t
)
e'
)
where
(
_
,
e'
)
=
convertSubExpr
scopes
e
(
t'
,
Cast
(
Left
t'
)
e'
)
where
e'
=
convertExpr
scopes
t
$
snd
$
convertSubExpr
scopes
e
t'
=
convertType
t
convertSubExpr
scopes
(
Pattern
items
)
=
if
all
(
==
Right
Nil
)
$
map
fst
items'
then
(
UnknownType
,
Concat
$
map
snd
items'
)
...
...
test/core/struct_pattern_cast.sv
View file @
fe90c7bb
...
...
@@ -29,4 +29,20 @@ module top;
$
display
(
"$bits(a.z.x) = %0d"
,
$
bits
(
a
.
z
.
x
))
;
$
display
(
"$bits(a.z.y) = %0d"
,
$
bits
(
a
.
z
.
y
))
;
end
typedef
struct
packed
{
logic
x
;
}
U
;
initial
begin
case
(
U
'
(
0
))
U
'
(
0
)
:
$
display
(
"1"
)
;
endcase
if
(
U
'
(
1
))
$
display
(
"2"
)
;
case
(
U
'
{
x
:
0
}
)
U
'
{
x
:
0
}:
$
display
(
"3"
)
;
endcase
if
(
U
'
{
x
:
1
}
)
$
display
(
"4"
)
;
end
endmodule
test/core/struct_pattern_cast.v
View file @
fe90c7bb
...
...
@@ -17,4 +17,11 @@ module top;
$
display
(
"$bits(a.z.x) = %0d"
,
32
)
;
$
display
(
"$bits(a.z.y) = %0d"
,
8
)
;
end
initial
begin
$
display
(
"1"
)
;
$
display
(
"2"
)
;
$
display
(
"3"
)
;
$
display
(
"4"
)
;
end
endmodule
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