basic conversion for int, byte, shortint, and longint

src/Convert.hs

@@ -16,6 +16,7 @@ import qualified Convert.Bits
 import qualified Convert.Enum
 import qualified Convert.FuncRet
 import qualified Convert.Interface
+import qualified Convert.IntTypes
 import qualified Convert.KWArgs
 import qualified Convert.Logic
 import qualified Convert.NamedBlock
@@ -41,6 +42,7 @@ phases excludes =
     , selectExclude (Job.Logic    , Convert.Logic.convert)
     , Convert.FuncRet.convert
     , Convert.Enum.convert
+    , Convert.IntTypes.convert
     , Convert.KWArgs.convert
     , Convert.PackedArray.convert
     , Convert.StarPort.convert

src/Convert/IntTypes.hs

+{- sv2v
+ - Author: Zachary Snow <zach@zachjs.com>
+ -
+ - Conversion for `int`, `shortint`, `longint`, and `byte`
+ -}
+
+module Convert.IntTypes (convert) where
+
+import Convert.Traverse
+import Language.SystemVerilog.AST
+
+convert :: [AST] -> [AST]
+convert =
+    map $
+    traverseDescriptions $
+    traverseModuleItems $
+    traverseTypes convertType
+
+convertType :: Type -> Type
+convertType (IntegerAtom TInt      sg) = baseType sg Signed      32
+convertType (IntegerAtom TShortint sg) = baseType sg Signed      16
+convertType (IntegerAtom TLongint  sg) = baseType sg Signed      64
+convertType (IntegerAtom TByte     sg) = baseType sg Unspecified  8
+convertType other = other
+
+-- makes a integer "compatible" type with the given signing, base signing and
+-- size; if not unspecified, the first signing overrides the second
+baseType :: Signing -> Signing -> Int -> Type
+baseType sgOverride sgBase size =
+    IntegerVector TReg sg [(Number hi, Number "0")]
+    where
+        hi = show (size - 1)
+        sg = if sgOverride /= Unspecified
+                then sgOverride
+                else sgBase

src/Convert/Logic.hs

@@ -7,6 +7,8 @@
  - initial block. Other module-level logics become wires. All other logics
  - (i.e., in a function) become regs.
  -
+ - Parameters and localparams with integer vector types become implicit.
+ -
  - The struct conversion and Verilog-2005's lack of permissive net vs. variable
  - resolution leads to some interesting special cases for this conversion, as
  - parts of a struct may be used as a variable, while other parts may be used as
@@ -110,7 +112,7 @@ convertDescription ports orig =
                                     ++ portName ++ " of " ++ instanceName
                 fixBinding other = (other, [])
         -- rewrite variable declarations to have the correct type
-        convertModuleItem (MIPackageItem (Decl (Variable dir (IntegerVector TLogic sg mr) ident a me))) =
+        convertModuleItem (MIPackageItem (Decl (Variable dir (IntegerVector _ sg mr) ident a me))) =
             MIPackageItem $ Decl $ Variable dir (t mr) ident a me
             where
                 t = if sg /= Unspecified || Set.member ident idents
@@ -119,9 +121,9 @@ convertDescription ports orig =
         convertModuleItem other = other
         -- all other logics (i.e. inside of functions) become regs
         convertDecl :: Decl -> Decl
-        convertDecl (Parameter  (IntegerVector TLogic sg rs) x e) =
+        convertDecl (Parameter  (IntegerVector _ sg rs) x e) =
             Parameter  (Implicit sg rs) x e
-        convertDecl (Localparam (IntegerVector TLogic sg rs) x e) =
+        convertDecl (Localparam (IntegerVector _ sg rs) x e) =
             Localparam (Implicit sg rs) x e
         convertDecl (Variable d (IntegerVector TLogic sg rs) x a me) =
             Variable d (IntegerVector TReg sg rs) x a me

sv2v.cabal

@@ -60,6 +60,7 @@ executable sv2v
     Convert.Enum
     Convert.FuncRet
     Convert.Interface
+    Convert.IntTypes
     Convert.KWArgs
     Convert.Logic
     Convert.NamedBlock