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lvzhengyang
sv2v
Commits
f8a2bcbe
Commit
f8a2bcbe
authored
Sep 11, 2019
by
Zachary Snow
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conversion for function void (resolves #32)
parent
6271e16b
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3 changed files
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15 additions
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2 deletions
+15
-2
src/Language/SystemVerilog/Parser/Parse.y
+3
-2
test/basic/function_void.sv
+6
-0
test/basic/function_void.v
+6
-0
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src/Language/SystemVerilog/Parser/Parse.y
View file @
f8a2bcbe
...
...
@@ -731,8 +731,9 @@ PackageItem :: { [PackageItem] }
| NonDeclPackageItem { $1 }
NonDeclPackageItem :: { [PackageItem] }
: "typedef" Type Identifier ";" { [Typedef $2 $3] }
| "function" opt(Lifetime) FuncRetAndName TFItems DeclsAndStmts "endfunction" opt(Tag) { [Function $2 (fst $3) (snd $3) (map defaultFuncInput $ (map makeInput $4) ++ fst $5) (snd $5)] }
| "task" opt(Lifetime) Identifier TFItems DeclsAndStmts "endtask" opt(Tag) { [Task $2 $3 (map defaultFuncInput $ $4 ++ fst $5) (snd $5)] }
| "function" opt(Lifetime) FuncRetAndName TFItems DeclsAndStmts "endfunction" opt(Tag) { [Function $2 (fst $3) (snd $3) (map defaultFuncInput $ (map makeInput $4) ++ fst $5) (snd $5)] }
| "function" opt(Lifetime) "void" Identifier TFItems DeclsAndStmts "endfunction" opt(Tag) { [Task $2 $4 (map defaultFuncInput $ $5 ++ fst $6) (snd $6)] }
| "task" opt(Lifetime) Identifier TFItems DeclsAndStmts "endtask" opt(Tag) { [Task $2 $3 (map defaultFuncInput $ $4 ++ fst $5) (snd $5)] }
| "import" PackageImportItems ";" { map (uncurry Import) $2 }
| "export" PackageImportItems ";" { map (Export . Just) $2 }
| "export" "*" "::" "*" ";" { [Export Nothing] } -- "Nothing" being no restrictions
...
...
test/basic/function_void.sv
0 → 100644
View file @
f8a2bcbe
module
top
;
function
void
foo
;
$
display
(
"foo called"
)
;
endfunction
initial
foo
;
endmodule
test/basic/function_void.v
0 → 100644
View file @
f8a2bcbe
module
top
;
task
foo
;
$
display
(
"foo called"
)
;
endtask
initial
foo
;
endmodule
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