fix simple delayed multi-pack conversion within interface

src/Convert/ImplicitNet.hs

@@ -61,7 +61,8 @@ traverseModuleItemM defaultNetType (orig @ (NOutputGate _ _ x lhss expr)) = do
     _ <- mapM (needsLHS defaultNetType) lhss
     needsExpr defaultNetType expr
     return orig
-traverseModuleItemM defaultNetType (orig @ (Instance _ _ _ _ ports)) = do
+traverseModuleItemM defaultNetType (orig @ (Instance _ _ x _ ports)) = do
+    insertElem x ()
     _ <- mapM (needsExpr defaultNetType . snd) ports
     return orig
 traverseModuleItemM _ item = return item

src/Convert/MultiplePacked.hs

@@ -39,8 +39,13 @@ import Language.SystemVerilog.AST
 type TypeInfo = (Type, [Range])
 
 convert :: [AST] -> [AST]
-convert = map $ traverseDescriptions $ partScoper
-    traverseDeclM traverseModuleItemM traverseGenItemM traverseStmtM
+convert = map $ traverseDescriptions convertDescription
+
+convertDescription :: Description -> Description
+convertDescription (description @ (Part _ _ Module _ _ _ _)) =
+    partScoper traverseDeclM traverseModuleItemM traverseGenItemM traverseStmtM
+    description
+convertDescription other = other
 
 -- collects and converts declarations with multiple packed dimensions
 traverseDeclM :: Decl -> Scoper TypeInfo Decl

test/basic/interface_delay_1.sv

+interface Interface;
+    logic [0:1][0:2] arr;
+endinterface
+
+module Module(intf);
+    Interface intf;
+endmodule
+
+module top;
+    Interface intf();
+    Module mod [1][2] (intf);
+    assign intf.arr[1] = 6;
+    assign intf.arr[0][0] = 1;
+    initial $display("%b", intf.arr);
+endmodule

test/basic/interface_delay_1.v

+module top;
+    if (1) begin : intf
+        wire [0:1][0:2] arr;
+    end
+    assign intf.arr[1] = 6;
+    assign intf.arr[0][0] = 1;
+    initial $display("%b", intf.arr);
+endmodule