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lvzhengyang
sv2v
Commits
f2ccebd5
Commit
f2ccebd5
authored
Jun 19, 2020
by
Zachary Snow
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release v0.0.4
parent
8d37db30
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src/Job.hs
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sv2v.cabal
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src/Job.hs
View file @
f2ccebd5
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@@ -54,7 +54,7 @@ defaultJob = Job
...
@@ -54,7 +54,7 @@ defaultJob = Job
,
verbose
=
nam
"verbose"
&=
help
"Retain certain conversion artifacts"
,
verbose
=
nam
"verbose"
&=
help
"Retain certain conversion artifacts"
}
}
&=
program
"sv2v"
&=
program
"sv2v"
&=
summary
(
"sv2v v0.0.
3
("
++
shortGitHash
++
")"
)
&=
summary
(
"sv2v v0.0.
4
("
++
shortGitHash
++
")"
)
&=
details
[
"sv2v converts SystemVerilog to Verilog."
&=
details
[
"sv2v converts SystemVerilog to Verilog."
,
"More info: https://github.com/zachjs/sv2v"
,
"More info: https://github.com/zachjs/sv2v"
,
"(C) 2019-2020 Zachary Snow, 2011-2015 Tom Hawkins"
]
,
"(C) 2019-2020 Zachary Snow, 2011-2015 Tom Hawkins"
]
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...
sv2v.cabal
View file @
f2ccebd5
cabal-version: 2.4
cabal-version: 2.4
name: sv2v
name: sv2v
version: 0.0.
3
version: 0.0.
4
synopsis: SystemVerilog to Verilog conversion
synopsis: SystemVerilog to Verilog conversion
description:
description:
A tool for coverting SystemVerilog to Verilog. Originally forked from the
A tool for coverting SystemVerilog to Verilog. Originally forked from the
...
...
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