support generate for without explicit block

src/Convert/AsgnOp.hs

@@ -19,8 +19,8 @@ convert =
     )
 
 convertGenItem :: GenItem -> GenItem
-convertGenItem (GenFor a b (ident, AsgnOp op, expr) c d) =
-    GenFor a b (ident, AsgnOpEq, BinOp op (Ident ident) expr) c d
+convertGenItem (GenFor a b (ident, AsgnOp op, expr) c) =
+    GenFor a b (ident, AsgnOpEq, BinOp op (Ident ident) expr) c
 convertGenItem other = other
 
 convertStmt :: Stmt -> Stmt

src/Convert/ForDecl.hs

@@ -22,14 +22,17 @@ convert =
     )
 
 convertGenItem :: GenItem -> GenItem
-convertGenItem (GenFor (True, x, e) a b bx c) =
+convertGenItem (GenFor (True, x, e) a b c) =
     GenBlock "" genItems
     where
+        bx = case c of
+            GenBlock name _ -> name
+            _ -> ""
         x' = if null bx then x else bx ++ "_" ++ x
         Generate genItems =
             traverseNestedModuleItems converter $ Generate $
             [ GenModuleItem $ Genvar x'
-            , GenFor (False, x, e) a b bx c
+            , GenFor (False, x, e) a b c
             ]
         converter =
             (traverseExprs $ traverseNestedExprs convertExpr) .

src/Convert/Traverse.hs

@@ -619,11 +619,11 @@ traverseExprsM' strat exprMapper = moduleItemMapper
         a'' <- traverseAssertionExprsM exprMapper a'
         return $ AssertionItem (mx, a'')
 
-    genItemMapper (GenFor (n1, x1, e1) cc (x2, op2, e2) mn subItems) = do
+    genItemMapper (GenFor (n1, x1, e1) cc (x2, op2, e2) subItem) = do
         e1' <- exprMapper e1
         e2' <- exprMapper e2
         cc' <- exprMapper cc
-        return $ GenFor (n1, x1, e1') cc' (x2, op2, e2') mn subItems
+        return $ GenFor (n1, x1, e1') cc' (x2, op2, e2') subItem
     genItemMapper (GenIf e i1 i2) = do
         e' <- exprMapper e
         return $ GenIf e' i1 i2
@@ -748,12 +748,12 @@ traverseLHSsM' strat mapper item =
             items' <- mapM (traverseNestedGenItemsM traverGenItemLHSsM) items
             return $ Generate items'
         traverseModuleItemLHSsM other = return other
-        traverGenItemLHSsM (GenFor (n1, x1, e1) cc (x2, op2, e2) mn subItems) = do
+        traverGenItemLHSsM (GenFor (n1, x1, e1) cc (x2, op2, e2) subItem) = do
             wrapped_x1' <- (if n1 then return else mapper) $ LHSIdent x1
             wrapped_x2' <- mapper $ LHSIdent x2
             let LHSIdent x1' = wrapped_x1'
             let LHSIdent x2' = wrapped_x2'
-            return $ GenFor (n1, x1', e1) cc (x2', op2, e2) mn subItems
+            return $ GenFor (n1, x1', e1) cc (x2', op2, e2) subItem
         traverGenItemLHSsM other = return other
 
 traverseLHSs' :: TFStrategy -> Mapper LHS -> Mapper ModuleItem
@@ -924,9 +924,9 @@ traverseSinglyNestedGenItemsM fullMapper = gim
         gim (GenBlock x subItems) = do
             subItems' <- mapM fullMapper subItems
             return $ GenBlock x (concatMap flattenBlocks subItems')
-        gim (GenFor a b c d subItems) = do
-            subItems' <- mapM fullMapper subItems
-            return $ GenFor a b c d (concatMap flattenBlocks subItems')
+        gim (GenFor a b c subItem) = do
+            subItem' <- fullMapper subItem
+            return $ GenFor a b c subItem'
         gim (GenIf e i1 i2) = do
             i1' <- fullMapper i1
             i2' <- fullMapper i2

src/Language/SystemVerilog/AST/GenItem.hs

@@ -22,7 +22,7 @@ import {-# SOURCE #-} Language.SystemVerilog.AST.ModuleItem (ModuleItem)
 data GenItem
     = GenBlock Identifier [GenItem]
     | GenCase  Expr [GenCase] (Maybe GenItem)
-    | GenFor   (Bool, Identifier, Expr) Expr (Identifier, AsgnOp, Expr) Identifier [GenItem]
+    | GenFor   (Bool, Identifier, Expr) Expr (Identifier, AsgnOp, Expr) GenItem
     | GenIf    Expr GenItem GenItem
     | GenNull
     | GenModuleItem ModuleItem
@@ -43,13 +43,13 @@ instance Show GenItem where
                 Just c -> printf "\n\tdefault: %s" (show c)
     show (GenIf e a GenNull) = printf "if (%s) %s"          (show e) (show a)
     show (GenIf e a b      ) = printf "if (%s) %s\nelse %s" (show e) (show a) (show b)
-    show (GenFor (new, x1, e1) c (x2, o2, e2) x is) =
+    show (GenFor (new, x1, e1) c (x2, o2, e2) s) =
         printf "for (%s%s = %s; %s; %s %s %s) %s"
             (if new then "genvar " else "")
             x1 (show e1)
             (show c)
             x2 (show o2) (show e2)
-            (show $ GenBlock x is)
+            (show s)
     show (GenNull) = ";"
     show (GenModuleItem item) = show item
 

src/Language/SystemVerilog/Parser/Parse.y

@@ -1189,7 +1189,7 @@ ConditionalGenerateConstruct :: { GenItem }
   | "if" "(" Expr ")" GenItemOrNull %prec NoElse         { GenIf $3 $5 GenNull }
   | "case" "(" Expr ")" GenCasesWithDefault "endcase"    { GenCase $3 (fst $5) (snd $5) }
 LoopGenerateConstruct :: { GenItem }
-  : "for" "(" GenvarInitialization ";" Expr ";" GenvarIteration ")" GenBlock { (uncurry $ GenFor $3 $5 $7) $9 }
+  : "for" "(" GenvarInitialization ";" Expr ";" GenvarIteration ")" GenItem { GenFor $3 $5 $7 $9 }
 
 GenBlock :: { (Identifier, [GenItem]) }
   : "begin" StrTag GenItems "end" StrTag { (combineTags $2 $5, $3) }

test/basic/for_decl.sv

@@ -64,4 +64,10 @@ module top;
     assign start = gen_filter[0].x;
     initial $display(start);
 
+    logic [0:31] c;
+    generate
+        for (genvar n = 0; n < 32; n = n + 1)
+            assign c[n] = n & 1;
+    endgenerate
+
 endmodule

test/basic/for_decl.v

@@ -75,4 +75,10 @@ module top;
     assign start = gen_filter[0].x;
     initial $display(start);
 
+    wire [0:31] c;
+    generate
+        for (n = 0; n < 32; n = n + 1)
+            assign c[n] = n & 1;
+    endgenerate
+
 endmodule