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lvzhengyang
sv2v
Commits
e88a6b9d
Commit
e88a6b9d
authored
Jul 20, 2020
by
Zachary Snow
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fix type lookup of yet-unresolved types (resolves #111)
parent
7eed2fc5
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3 changed files
with
36 additions
and
2 deletions
+36
-2
src/Convert/TypeOf.hs
+4
-2
test/basic/typeof_alias.sv
+18
-0
test/basic/typeof_alias.v
+14
-0
No files found.
src/Convert/TypeOf.hs
View file @
e88a6b9d
...
...
@@ -90,12 +90,14 @@ typeof (Call (Ident x) _) =
typeof
(
orig
@
(
Bit
e
_
))
=
do
t
<-
typeof
e
case
t
of
TypeOf
_
->
lookupTypeOf
orig
TypeOf
{}
->
lookupTypeOf
orig
Alias
{}
->
return
$
TypeOf
orig
_
->
return
$
popRange
t
typeof
(
orig
@
(
Range
e
mode
r
))
=
do
t
<-
typeof
e
return
$
case
t
of
TypeOf
_
->
TypeOf
orig
TypeOf
{}
->
TypeOf
orig
Alias
{}
->
TypeOf
orig
_
->
replaceRange
(
lo
,
hi
)
t
where
lo
=
fst
r
...
...
test/basic/typeof_alias.sv
0 → 100644
View file @
e88a6b9d
package
P
;
typedef
logic
[
1
:
0
][
2
:
0
]
T
;
endpackage
module
top
;
P
::
T
w
;
type
(
w
[
0
])
x
;
type
(
x
[
0
])
y
;
type
(
w
[
0
][
0
])
z
;
type
(
w
[
1
:
0
])
a
;
type
(
w
[
0
][
1
:
0
])
b
;
initial
begin
$
display
(
"%b %b %b %b"
,
w
,
x
,
y
,
z
)
;
$
display
(
"%b %b"
,
a
,
b
)
;
end
endmodule
test/basic/typeof_alias.v
0 → 100644
View file @
e88a6b9d
module
top
;
wire
[
5
:
0
]
w
;
wire
[
2
:
0
]
x
;
wire
y
;
wire
z
;
wire
[
5
:
0
]
a
;
wire
[
1
:
0
]
b
;
initial
begin
$
display
(
"%b %b %b %b"
,
w
,
x
,
y
,
z
)
;
$
display
(
"%b %b"
,
a
,
b
)
;
end
endmodule
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