omit reference file for verilog-compatible test inputs

test/basic/attr.v

-`include "attr.sv"

test/basic/div.v

-`include "div.sv"

test/basic/else_prec.v

-// Reference file is already plain Verilog
-`include "else_prec.sv"

test/basic/flatten.v

-// iverilog supports multi-dimensional packed arrays
-`include "flatten.sv"

test/basic/flatten_three.v

-// iverilog supports multi-dimensional packed arrays
-`include "flatten_three.sv"

test/basic/gate.v

-// This test is for parser coverge only.
-`include "gate.sv"

test/basic/packed_array_shadow.v

-// iverilog has support for packed arrays and functions
-`include "packed_array_shadow.sv"

test/basic/shift.v

-`include "shift.sv"

test/basic/stmt_task.v

-`include "stmt_task.sv"

test/basic/typeof_op.v

-`include "typeof_op.sv"

test/lex/cond.v

-// use iverilog as reference
-`include "cond.sv"

test/lex/file_line.v

-// use iverilog as reference
-`include "file_line.sv"

test/lex/macro_boundary.v

-`include "macro_boundary.sv"

test/lex/macro_iv.v

-// use iverilog as reference
-`include "macro_iv.sv"

test/lex/macro_string.v

-`include "macro_string.sv"

test/lex/macro_whitespace.v

-`include "macro_whitespace.sv"

test/lex/no_newline.v

-`include "no_newline.vh"
-module top;
-`ifdef A
-    initial $display("A is defined!");
-`endif
-endmodule

test/lex/number.v

-`include "number.sv"

test/lib/functions.sh

@@ -85,7 +85,14 @@ simpleTest() {
     tb=$3
 
     assertConverts $sv
-    assertConverts $ve
+
+    # some tests use inputs compatible with iverilog directly and so omit the
+    # reference manually converted file
+    if [ ! -f $ve ]; then
+        ve=$sv
+    else
+        assertConverts $ve
+    fi
 
     # some tests don't have a separate testbench, instead having the top-level
     # module defined in both of the input files