Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
S
sv2v
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
sv2v
Commits
df3620d3
Commit
df3620d3
authored
Sep 17, 2019
by
Zachary Snow
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
fix premature logic to wire conversion
parent
82218848
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
15 additions
and
8 deletions
+15
-8
src/Convert/Logic.hs
+15
-8
No files found.
src/Convert/Logic.hs
View file @
df3620d3
...
...
@@ -60,7 +60,7 @@ convert =
convertDescription
::
Ports
->
Description
->
Description
convertDescription
ports
orig
=
if
shouldConvert
then
traverseModuleItems
conversion
orig
then
converted
else
orig
where
shouldConvert
=
case
orig
of
...
...
@@ -69,18 +69,23 @@ convertDescription ports orig =
PackageItem
_
->
True
Package
_
_
_
->
False
Directive
_
->
False
origIdents
=
execWriter
(
collectModuleItemsM
regIdents
orig
)
fixed
=
traverseModuleItems
fixModuleItem
orig
fixedIdents
=
execWriter
(
collectModuleItemsM
regIdents
fixed
)
conversion
=
traverseDecls
convertDecl
.
convertModuleItem
idents
=
execWriter
(
collectModuleItemsM
regIdents
orig
)
convertModuleItem
::
ModuleItem
->
ModuleItem
converted
=
traverseModuleItems
conversion
fixed
fixModuleItem
::
ModuleItem
->
ModuleItem
-- rewrite bad continuous assignments to use procedural assignments
convert
ModuleItem
(
Assign
Nothing
lhs
expr
)
=
if
Set
.
disjoint
usedIdents
i
dents
fix
ModuleItem
(
Assign
Nothing
lhs
expr
)
=
if
Set
.
disjoint
usedIdents
origI
dents
then
Assign
Nothing
lhs
expr
else
AlwaysC
AlwaysComb
$
AsgnBlk
AsgnOpEq
lhs
expr
where
usedIdents
=
execWriter
$
collectNestedLHSsM
lhsIdents
lhs
-- rewrite port bindings to use temporary nets where necessary
convert
ModuleItem
(
Instance
moduleName
params
instanceName
rs
bindings
)
=
fix
ModuleItem
(
Instance
moduleName
params
instanceName
rs
bindings
)
=
if
null
newItems
then
Instance
moduleName
params
instanceName
rs
bindings
else
Generate
$
map
GenModuleItem
$
...
...
@@ -92,7 +97,7 @@ convertDescription ports orig =
newItems
=
concat
newItemsList
fixBinding
::
PortBinding
->
(
PortBinding
,
[
ModuleItem
])
fixBinding
(
portName
,
Just
expr
)
=
if
portDir
/=
Just
Output
||
Set
.
disjoint
usedIdents
i
dents
if
portDir
/=
Just
Output
||
Set
.
disjoint
usedIdents
origI
dents
then
((
portName
,
Just
expr
),
[]
)
else
((
portName
,
Just
tmpExpr
),
items
)
where
...
...
@@ -112,11 +117,13 @@ convertDescription ports orig =
++
show
expr
++
" connected to output port "
++
portName
++
" of "
++
instanceName
fixBinding
other
=
(
other
,
[]
)
fixModuleItem
other
=
other
-- rewrite variable declarations to have the correct type
convertModuleItem
(
MIPackageItem
(
Decl
(
Variable
dir
(
IntegerVector
_
sg
mr
)
ident
a
me
)))
=
MIPackageItem
$
Decl
$
Variable
dir
(
t
mr
)
ident
a
me
where
t
=
if
sg
/=
Unspecified
||
Set
.
member
ident
i
dents
t
=
if
Set
.
member
ident
fixedI
dents
then
IntegerVector
TReg
sg
else
Net
TWire
sg
convertModuleItem
other
=
other
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment