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lvzhengyang
sv2v
Commits
d34dc7df
Commit
d34dc7df
authored
Feb 17, 2019
by
Zachary Snow
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support for arithmetic shifts
parent
d4c6c0d0
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2 changed files
with
7 additions
and
1 deletions
+7
-1
Language/SystemVerilog/AST.hs
+4
-0
Language/SystemVerilog/Parser/Parse.y
+3
-1
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Language/SystemVerilog/AST.hs
View file @
d34dc7df
...
...
@@ -228,6 +228,8 @@ data BinOp
|
Le
|
Gt
|
Ge
|
ShiftAL
|
ShiftAR
deriving
Eq
instance
Show
BinOp
where
...
...
@@ -250,6 +252,8 @@ instance Show BinOp where
Le
->
"<="
Gt
->
">"
Ge
->
">="
ShiftAL
->
"<<<"
ShiftAR
->
">>>"
instance
Show
Expr
where
show
x
=
case
x
of
...
...
Language/SystemVerilog/Parser/Parse.y
View file @
d34dc7df
...
...
@@ -148,7 +148,7 @@ string { Token Lit_string _ _ }
%left "&" "~&"
%left "==" "!=" "===" "!=="
%left "<" "<=" ">" ">="
%left "<<" ">>"
%left "<<" ">>"
"<<<" ">>>"
%left "+" "-"
%left "*" "/" "%"
%left UPlus UMinus "!" "~" RedOps
...
...
@@ -420,6 +420,8 @@ Expr :: { Expr }
| Expr "*" Expr { BinOp Mul $1 $3 }
| Expr "/" Expr { BinOp Div $1 $3 }
| Expr "%" Expr { BinOp Mod $1 $3 }
| Expr "<<<" Expr { BinOp ShiftAL $1 $3 }
| Expr ">>>" Expr { BinOp ShiftAR $1 $3 }
| "!" Expr { UniOp Not $2 }
| "~" Expr { UniOp BWNot $2 }
| "+" Expr %prec UPlus { UniOp UAdd $2 }
...
...
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