Commit d2a18e01 by Zachary Snow

replace integer unsigned with size-32 reg

parent 36fcce89
......@@ -24,4 +24,6 @@ convertType :: Type -> Type
convertType (Implicit Unsigned rs) = Implicit Unspecified rs
convertType (IntegerVector t Unsigned rs) = IntegerVector t Unspecified rs
convertType (Net t Unsigned rs) = Net t Unspecified rs
convertType (IntegerAtom TInteger Unsigned) =
IntegerVector TReg Unspecified [(RawNum 31, RawNum 0)]
convertType other = other
`define MAKE_PRIM(typ, base, size) \
base [size-1:0] typ``_unspecified = 1; \
base unsigned [size-1:0] typ``_unsigned = 1; \
base [size-1:0] typ``_unsigned = 1; \
base signed [size-1:0] typ``_signed = 1;
module top;
......@@ -18,8 +18,8 @@ module top;
`MAKE_PRIM(shortint, reg, 16)
`MAKE_PRIM(int, reg, 32)
integer integer_unspecified = 1;
integer unsigned integer_unsigned = 1;
integer signed integer_signed = 1;
reg [31:0] integer_unsigned = 1;
integer integer_signed = 1;
`MAKE_PRIM(longint, reg, 64)
`MAKE_PRIM(bit, wire, 1)
......
......@@ -54,8 +54,8 @@ assertConverts() {
assertTrue "2nd conversion of $ac_file failed" $?
diff $ac_tmpa $ac_tmpb > /dev/null
assertTrue "conversion of $ac_file not stable after the first iteration" $?
# using sed to remove quoted strings and integer unsigned
filtered=`sed -E -e 's/"([^"]|\")+"//g' -e 's/integer unsigned/integer/g' $ac_tmpa`
# using sed to remove quoted strings
filtered=`sed -E 's/"([^"]|\")+"//g' $ac_tmpa`
# check for various things iverilog accepts which we don't want to output
prefix="conversion of $ac_file still contains"
assertNotMatch "$filtered" "$prefix dimension queries" \
......
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