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lvzhengyang
sv2v
Commits
cb42f37b
Commit
cb42f37b
authored
Feb 10, 2019
by
Zachary Snow
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removed support for inital and delays
parent
767b05cd
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2 changed files
with
0 additions
and
6 deletions
+0
-6
Language/SystemVerilog/AST.hs
+0
-4
Language/SystemVerilog/Parser/Parse.y
+0
-2
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Language/SystemVerilog/AST.hs
View file @
cb42f37b
...
@@ -79,7 +79,6 @@ data ModuleItem
...
@@ -79,7 +79,6 @@ data ModuleItem
|
PortDecl
Direction
(
Maybe
Range
)
Identifier
|
PortDecl
Direction
(
Maybe
Range
)
Identifier
|
LocalNet
Type
Identifier
(
Maybe
Expr
)
|
LocalNet
Type
Identifier
(
Maybe
Expr
)
|
Integer
[
Identifier
]
|
Integer
[
Identifier
]
|
Initial
Stmt
|
Always
(
Maybe
Sense
)
Stmt
|
Always
(
Maybe
Sense
)
Stmt
|
Assign
LHS
Expr
|
Assign
LHS
Expr
|
Instance
Identifier
[
PortBinding
]
Identifier
[
PortBinding
]
|
Instance
Identifier
[
PortBinding
]
Identifier
[
PortBinding
]
...
@@ -100,7 +99,6 @@ instance Show ModuleItem where
...
@@ -100,7 +99,6 @@ instance Show ModuleItem where
then
""
then
""
else
" = "
++
show
(
fromJust
v
)
else
" = "
++
show
(
fromJust
v
)
Integer
a
->
printf
"integer %s;"
$
commas
a
Integer
a
->
printf
"integer %s;"
$
commas
a
Initial
a
->
printf
"initial
\n
%s"
$
indent
$
show
a
Always
Nothing
b
->
printf
"always
\n
%s"
$
indent
$
show
b
Always
Nothing
b
->
printf
"always
\n
%s"
$
indent
$
show
b
Always
(
Just
a
)
b
->
printf
"always @(%s)
\n
%s"
(
show
a
)
$
indent
$
show
b
Always
(
Just
a
)
b
->
printf
"always @(%s)
\n
%s"
(
show
a
)
$
indent
$
show
b
Assign
a
b
->
printf
"assign %s = %s;"
(
show
a
)
(
show
b
)
Assign
a
b
->
printf
"assign %s = %s;"
(
show
a
)
(
show
b
)
...
@@ -292,7 +290,6 @@ data Stmt
...
@@ -292,7 +290,6 @@ data Stmt
|
For
(
Identifier
,
Expr
)
Expr
(
Identifier
,
Expr
)
Stmt
|
For
(
Identifier
,
Expr
)
Expr
(
Identifier
,
Expr
)
Stmt
|
If
Expr
Stmt
Stmt
|
If
Expr
Stmt
Stmt
|
StmtCall
Call
|
StmtCall
Call
|
Delay
Expr
Stmt
|
Null
|
Null
deriving
Eq
deriving
Eq
...
@@ -312,7 +309,6 @@ instance Show Stmt where
...
@@ -312,7 +309,6 @@ instance Show Stmt where
show
(
If
a
b
Null
)
=
printf
"if (%s)
\n
%s"
(
show
a
)
(
indent
$
show
b
)
show
(
If
a
b
Null
)
=
printf
"if (%s)
\n
%s"
(
show
a
)
(
indent
$
show
b
)
show
(
If
a
b
c
)
=
printf
"if (%s)
\n
%s
\n
else
\n
%s"
(
show
a
)
(
indent
$
show
b
)
(
indent
$
show
c
)
show
(
If
a
b
c
)
=
printf
"if (%s)
\n
%s
\n
else
\n
%s"
(
show
a
)
(
indent
$
show
b
)
(
indent
$
show
c
)
show
(
StmtCall
a
)
=
printf
"%s;"
(
show
a
)
show
(
StmtCall
a
)
=
printf
"%s;"
(
show
a
)
show
(
Delay
a
b
)
=
printf
"#%s %s"
(
showExprConst
a
)
(
show
b
)
show
(
Null
)
=
";"
show
(
Null
)
=
";"
type
Case
=
([
Expr
],
Stmt
)
type
Case
=
([
Expr
],
Stmt
)
...
...
Language/SystemVerilog/Parser/Parse.y
View file @
cb42f37b
...
@@ -218,7 +218,6 @@ ModuleItem :: { [ModuleItem] }
...
@@ -218,7 +218,6 @@ ModuleItem :: { [ModuleItem] }
| "wire" MaybeRange WireDeclarations ";" { map (uncurry $ LocalNet $ Wire $2) $3 }
| "wire" MaybeRange WireDeclarations ";" { map (uncurry $ LocalNet $ Wire $2) $3 }
| "integer" Identifiers ";" { [Integer $2] }
| "integer" Identifiers ";" { [Integer $2] }
| "assign" LHS "=" Expr ";" { [Assign $2 $4] }
| "assign" LHS "=" Expr ";" { [Assign $2 $4] }
| "initial" Stmt { [Initial $2] }
| "always" Stmt { [Always Nothing $2] }
| "always" Stmt { [Always Nothing $2] }
| "always" "@" "(" Sense ")" Stmt { [Always (Just $4) $6] }
| "always" "@" "(" Sense ")" Stmt { [Always (Just $4) $6] }
| "always" "@" "(" "*" ")" Stmt { [Always (Just SenseStar) $6] }
| "always" "@" "(" "*" ")" Stmt { [Always (Just SenseStar) $6] }
...
@@ -295,7 +294,6 @@ Stmt :: { Stmt }
...
@@ -295,7 +294,6 @@ Stmt :: { Stmt }
| "for" "(" Identifier "=" Expr ";" Expr ";" Identifier "=" Expr ")" Stmt { For ($3, $5) $7 ($9, $11) $13 }
| "for" "(" Identifier "=" Expr ";" Expr ";" Identifier "=" Expr ")" Stmt { For ($3, $5) $7 ($9, $11) $13 }
| LHS "=" Expr ";" { BlockingAssignment $1 $3 }
| LHS "=" Expr ";" { BlockingAssignment $1 $3 }
| LHS "<=" Expr ";" { NonBlockingAssignment $1 $3 }
| LHS "<=" Expr ";" { NonBlockingAssignment $1 $3 }
| "#" Expr Stmt { Delay $2 $3 }
| Call ";" { StmtCall $1 }
| Call ";" { StmtCall $1 }
| "case" "(" Expr ")" Cases CaseDefault "endcase" { Case $3 $5 $6 }
| "case" "(" Expr ")" Cases CaseDefault "endcase" { Case $3 $5 $6 }
...
...
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