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lvzhengyang
sv2v
Commits
c4f5718f
Commit
c4f5718f
authored
Mar 30, 2019
by
Zachary Snow
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support for binary xnor
parent
2314f97a
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2 changed files
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5 additions
and
1 deletions
+5
-1
src/Language/SystemVerilog/AST/Op.hs
+2
-0
src/Language/SystemVerilog/Parser/Parse.y
+3
-1
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src/Language/SystemVerilog/AST/Op.hs
View file @
c4f5718f
...
@@ -41,6 +41,7 @@ data BinOp
...
@@ -41,6 +41,7 @@ data BinOp
|
LogOr
|
LogOr
|
BitAnd
|
BitAnd
|
BitXor
|
BitXor
|
BitXnor
|
BitOr
|
BitOr
|
Mul
|
Mul
|
Div
|
Div
...
@@ -69,6 +70,7 @@ instance Show BinOp where
...
@@ -69,6 +70,7 @@ instance Show BinOp where
show
LogOr
=
"||"
show
LogOr
=
"||"
show
BitAnd
=
"&"
show
BitAnd
=
"&"
show
BitXor
=
"^"
show
BitXor
=
"^"
show
BitXnor
=
"~^"
show
BitOr
=
"|"
show
BitOr
=
"|"
show
Mul
=
"*"
show
Mul
=
"*"
show
Div
=
"/"
show
Div
=
"/"
...
...
src/Language/SystemVerilog/Parser/Parse.y
View file @
c4f5718f
...
@@ -221,7 +221,7 @@ directive { Token Spe_Directive _ _ }
...
@@ -221,7 +221,7 @@ directive { Token Spe_Directive _ _ }
%left "||"
%left "||"
%left "&&"
%left "&&"
%left "|" "~|"
%left "|" "~|"
%left "^" "^~"
%left "^" "^~"
"~^"
%left "&" "~&"
%left "&" "~&"
%left "==" "!=" "===" "!==" "==?" "!=?"
%left "==" "!=" "===" "!==" "==?" "!=?"
%left "<" "<=" ">" ">="
%left "<" "<=" ">" ">="
...
@@ -781,6 +781,8 @@ Expr :: { Expr }
...
@@ -781,6 +781,8 @@ Expr :: { Expr }
| Expr "|" Expr { BinOp BitOr $1 $3 }
| Expr "|" Expr { BinOp BitOr $1 $3 }
| Expr "^" Expr { BinOp BitXor $1 $3 }
| Expr "^" Expr { BinOp BitXor $1 $3 }
| Expr "&" Expr { BinOp BitAnd $1 $3 }
| Expr "&" Expr { BinOp BitAnd $1 $3 }
| Expr "~^" Expr { BinOp BitXnor $1 $3 }
| Expr "^~" Expr { BinOp BitXnor $1 $3 }
| Expr "+" Expr { BinOp Add $1 $3 }
| Expr "+" Expr { BinOp Add $1 $3 }
| Expr "-" Expr { BinOp Sub $1 $3 }
| Expr "-" Expr { BinOp Sub $1 $3 }
| Expr "*" Expr { BinOp Mul $1 $3 }
| Expr "*" Expr { BinOp Mul $1 $3 }
...
...
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