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Commit bfafea5d by Zachary Snow
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Fix compiliation; trailing whitespace; added .gitignore

parent 363ca80a
Showing with 261 additions and 252 deletions
.gitignore 0 → 100644
*.swp
dist/
Data/BitVec.hs
...@@ -8,6 +8,7 @@ module Data.BitVec ...@@ -8,6 +8,7 @@ module Data.BitVec
) where ) where
import Data.Bits import Data.Bits
import Data.Semigroup
data BitVec = BitVec Int Integer deriving (Show, Eq) data BitVec = BitVec Int Integer deriving (Show, Eq)
...@@ -39,6 +40,9 @@ instance Bits BitVec where ...@@ -39,6 +40,9 @@ instance Bits BitVec where
isSigned _ = False isSigned _ = False
popCount (BitVec _ v) = popCount v popCount (BitVec _ v) = popCount v
instance Semigroup BitVec where
(<>) = mappend
instance Monoid BitVec where instance Monoid BitVec where
mempty = BitVec 0 0 mempty = BitVec 0 0
mappend (BitVec w1 v1) (BitVec w2 v2) = BitVec (w1 + w2) (shiftL v1 w2 .|. v2) mappend (BitVec w1 v1) (BitVec w2 v2) = BitVec (w1 + w2) (shiftL v1 w2 .|. v2)
......
Language/Verilog/AST.hs
...@@ -17,6 +17,7 @@ module Language.Verilog.AST ...@@ -17,6 +17,7 @@ module Language.Verilog.AST
import Data.Bits import Data.Bits
import Data.List import Data.List
import Data.Maybe import Data.Maybe
import Data.Semigroup
import Text.Printf import Text.Printf
import Data.BitVec import Data.BitVec
...@@ -75,7 +76,7 @@ instance Show ModuleItem where ...@@ -75,7 +76,7 @@ instance Show ModuleItem where
showAssign a = case a of showAssign a = case a of
Nothing -> "" Nothing -> ""
Just a -> printf " = %s" $ show a Just a -> printf " = %s" $ show a
showRange :: Maybe Range -> String showRange :: Maybe Range -> String
showRange Nothing = "" showRange Nothing = ""
showRange (Just (h, l)) = printf "[%s:%s] " (showExprConst h) (showExprConst l) showRange (Just (h, l)) = printf "[%s:%s] " (showExprConst h) (showExprConst l)
...@@ -117,24 +118,24 @@ instance Show UniOp where ...@@ -117,24 +118,24 @@ instance Show UniOp where
USub -> "-" USub -> "-"
data BinOp data BinOp
= And = And
| Or | Or
| BWAnd | BWAnd
| BWXor | BWXor
| BWOr | BWOr
| Mul | Mul
| Div | Div
| Mod | Mod
| Add | Add
| Sub | Sub
| ShiftL | ShiftL
| ShiftR | ShiftR
| Eq | Eq
| Ne | Ne
| Lt | Lt
| Le | Le
| Gt | Gt
| Ge | Ge
deriving Eq deriving Eq
instance Show BinOp where instance Show BinOp where
...@@ -210,6 +211,8 @@ instance Bits Expr where ...@@ -210,6 +211,8 @@ instance Bits Expr where
bit = error "Not supported: bit" bit = error "Not supported: bit"
popCount = error "Not supported: popCount" popCount = error "Not supported: popCount"
instance Semigroup Expr where
(<>) = mappend
instance Monoid Expr where instance Monoid Expr where
mempty = 0 mempty = 0
......
Language/Verilog/Parser/Lex.x
...@@ -38,7 +38,7 @@ $decimalDigit = [0-9] ...@@ -38,7 +38,7 @@ $decimalDigit = [0-9]
@binaryNumber = @size? @binaryBase @binaryValue @binaryNumber = @size? @binaryBase @binaryValue
@octalNumber = @size? @octalBase @octalValue @octalNumber = @size? @octalBase @octalValue
@hexNumber = @size? @hexBase @hexValue @hexNumber = @size? @hexBase @hexValue
-- $exp = [eE] -- $exp = [eE]
-- $sign = [\+\-] -- $sign = [\+\-]
-- @realNumber = unsignedNumber "." unsignedNumber | unsignedNumber ( "." unsignedNumber)? exp sign? unsignedNumber -- @realNumber = unsignedNumber "." unsignedNumber | unsignedNumber ( "." unsignedNumber)? exp sign? unsignedNumber
......
Language/Verilog/Parser/Parse.y
...@@ -221,7 +221,7 @@ LHS :: { LHS } ...@@ -221,7 +221,7 @@ LHS :: { LHS }
| "{" LHSs "}" { LHSConcat $2 } | "{" LHSs "}" { LHSConcat $2 }
LHSs :: { [LHS] } LHSs :: { [LHS] }
: LHS { [$1] } : LHS { [$1] }
| LHSs "," LHS { $1 ++ [$3] } | LHSs "," LHS { $1 ++ [$3] }
Sense :: { Sense } Sense :: { Sense }
...@@ -356,7 +356,7 @@ toNumber = number . tokenString ...@@ -356,7 +356,7 @@ toNumber = number . tokenString
where where
w = takeWhile (/= '\'') a w = takeWhile (/= '\'') a
b = dropWhile (/= '\'') a b = dropWhile (/= '\'') a
f a f a
| isPrefixOf "'d" a = read $ drop 2 a | isPrefixOf "'d" a = read $ drop 2 a
| isPrefixOf "'h" a = read $ "0x" ++ drop 2 a | isPrefixOf "'h" a = read $ "0x" ++ drop 2 a
| isPrefixOf "'b" a = foldl (\ n b -> shiftL n 1 .|. (if b == '1' then 1 else 0)) 0 (drop 2 a) | isPrefixOf "'b" a = foldl (\ n b -> shiftL n 1 .|. (if b == '1' then 1 else 0)) 0 (drop 2 a)
......
Language/Verilog/Parser/Preprocess.hs
...@@ -16,7 +16,7 @@ uncomment file a = uncomment a ...@@ -16,7 +16,7 @@ uncomment file a = uncomment a
removeEOL a = case a of removeEOL a = case a of
"" -> "" "" -> ""
'\n' : rest -> '\n' : uncomment rest '\n' : rest -> '\n' : uncomment rest
'\t' : rest -> '\t' : removeEOL rest '\t' : rest -> '\t' : removeEOL rest
_ : rest -> ' ' : removeEOL rest _ : rest -> ' ' : removeEOL rest
...@@ -42,7 +42,7 @@ uncomment file a = uncomment a ...@@ -42,7 +42,7 @@ uncomment file a = uncomment a
'\\' : '"' : rest -> "\\\"" ++ ignoreString rest '\\' : '"' : rest -> "\\\"" ++ ignoreString rest
a : rest -> a : ignoreString rest a : rest -> a : ignoreString rest
-- | A simple `define preprocessor. -- | A simple `define preprocessor.
preprocess :: [(String, String)] -> FilePath -> String -> String preprocess :: [(String, String)] -> FilePath -> String -> String
preprocess env file content = unlines $ pp True [] env $ lines $ uncomment file content preprocess env file content = unlines $ pp True [] env $ lines $ uncomment file content
where where
...@@ -50,8 +50,8 @@ preprocess env file content = unlines $ pp True [] env $ lines $ uncomment file ...@@ -50,8 +50,8 @@ preprocess env file content = unlines $ pp True [] env $ lines $ uncomment file
pp _ _ _ [] = [] pp _ _ _ [] = []
pp on stack env (a : rest) = case words a of pp on stack env (a : rest) = case words a of
"`define" : name : value -> "" : pp on stack (if on then (name, ppLine env $ unwords value) : env else env) rest "`define" : name : value -> "" : pp on stack (if on then (name, ppLine env $ unwords value) : env else env) rest
"`ifdef" : name : _ -> "" : pp (on && (elem name $ fst $ unzip env)) (on : stack) env rest "`ifdef" : name : _ -> "" : pp (on && (elem name $ fst $ unzip env)) (on : stack) env rest
"`ifndef" : name : _ -> "" : pp (on && (notElem name $ fst $ unzip env)) (on : stack) env rest "`ifndef" : name : _ -> "" : pp (on && (notElem name $ fst $ unzip env)) (on : stack) env rest
"`else" : _ "`else" : _
| not $ null stack -> "" : pp (head stack && not on) stack env rest | not $ null stack -> "" : pp (head stack && not on) stack env rest
| otherwise -> error $ "`else without associated `ifdef/`ifndef: " ++ file | otherwise -> error $ "`else without associated `ifdef/`ifndef: " ++ file
......
Language/Verilog/Parser/Tokens.hs
...@@ -18,232 +18,232 @@ instance Show Position where ...@@ -18,232 +18,232 @@ instance Show Position where
data Token = Token TokenName String Position deriving (Show, Eq) data Token = Token TokenName String Position deriving (Show, Eq)
data TokenName data TokenName
= KW_alias = KW_alias
| KW_always | KW_always
| KW_always_comb | KW_always_comb
| KW_always_ff | KW_always_ff
| KW_always_latch | KW_always_latch
| KW_and | KW_and
| KW_assert | KW_assert
| KW_assign | KW_assign
| KW_assume | KW_assume
| KW_automatic | KW_automatic
| KW_before | KW_before
| KW_begin | KW_begin
| KW_bind | KW_bind
| KW_bins | KW_bins
| KW_binsof | KW_binsof
| KW_bit | KW_bit
| KW_break | KW_break
| KW_buf | KW_buf
| KW_bufif0 | KW_bufif0
| KW_bufif1 | KW_bufif1
| KW_byte | KW_byte
| KW_case | KW_case
| KW_casex | KW_casex
| KW_casez | KW_casez
| KW_cell | KW_cell
| KW_chandle | KW_chandle
| KW_class | KW_class
| KW_clocking | KW_clocking
| KW_cmos | KW_cmos
| KW_config | KW_config
| KW_const | KW_const
| KW_constraint | KW_constraint
| KW_context | KW_context
| KW_continue | KW_continue
| KW_cover | KW_cover
| KW_covergroup | KW_covergroup
| KW_coverpoint | KW_coverpoint
| KW_cross | KW_cross
| KW_deassign | KW_deassign
| KW_default | KW_default
| KW_defparam | KW_defparam
| KW_design | KW_design
| KW_disable | KW_disable
| KW_dist | KW_dist
| KW_do | KW_do
| KW_edge | KW_edge
| KW_else | KW_else
| KW_end | KW_end
| KW_endcase | KW_endcase
| KW_endclass | KW_endclass
| KW_endclocking | KW_endclocking
| KW_endconfig | KW_endconfig
| KW_endfunction | KW_endfunction
| KW_endgenerate | KW_endgenerate
| KW_endgroup | KW_endgroup
| KW_endinterface | KW_endinterface
| KW_endmodule | KW_endmodule
| KW_endpackage | KW_endpackage
| KW_endprimitive | KW_endprimitive
| KW_endprogram | KW_endprogram
| KW_endproperty | KW_endproperty
| KW_endspecify | KW_endspecify
| KW_endsequence | KW_endsequence
| KW_endtable | KW_endtable
| KW_endtask | KW_endtask
| KW_enum | KW_enum
| KW_event | KW_event
| KW_expect | KW_expect
| KW_export | KW_export
| KW_extends | KW_extends
| KW_extern | KW_extern
| KW_final | KW_final
| KW_first_match | KW_first_match
| KW_for | KW_for
| KW_force | KW_force
| KW_foreach | KW_foreach
| KW_forever | KW_forever
| KW_fork | KW_fork
| KW_forkjoin | KW_forkjoin
| KW_function | KW_function
| KW_function_prototype | KW_function_prototype
| KW_generate | KW_generate
| KW_genvar | KW_genvar
| KW_highz0 | KW_highz0
| KW_highz1 | KW_highz1
| KW_if | KW_if
| KW_iff | KW_iff
| KW_ifnone | KW_ifnone
| KW_ignore_bins | KW_ignore_bins
| KW_illegal_bins | KW_illegal_bins
| KW_import | KW_import
| KW_incdir | KW_incdir
| KW_include | KW_include
| KW_initial | KW_initial
| KW_inout | KW_inout
| KW_input | KW_input
| KW_inside | KW_inside
| KW_instance | KW_instance
| KW_int | KW_int
| KW_integer | KW_integer
| KW_interface | KW_interface
| KW_intersect | KW_intersect
| KW_join | KW_join
| KW_join_any | KW_join_any
| KW_join_none | KW_join_none
| KW_large | KW_large
| KW_liblist | KW_liblist
| KW_library | KW_library
| KW_local | KW_local
| KW_localparam | KW_localparam
| KW_logic | KW_logic
| KW_longint | KW_longint
| KW_macromodule | KW_macromodule
| KW_matches | KW_matches
| KW_medium | KW_medium
| KW_modport | KW_modport
| KW_module | KW_module
| KW_nand | KW_nand
| KW_negedge | KW_negedge
| KW_new | KW_new
| KW_nmos | KW_nmos
| KW_nor | KW_nor
| KW_noshowcancelled | KW_noshowcancelled
| KW_not | KW_not
| KW_notif0 | KW_notif0
| KW_notif1 | KW_notif1
| KW_null | KW_null
| KW_option | KW_option
| KW_or | KW_or
| KW_output | KW_output
| KW_package | KW_package
| KW_packed | KW_packed
| KW_parameter | KW_parameter
| KW_pathpulse_dollar | KW_pathpulse_dollar
| KW_pmos | KW_pmos
| KW_posedge | KW_posedge
| KW_primitive | KW_primitive
| KW_priority | KW_priority
| KW_program | KW_program
| KW_property | KW_property
| KW_protected | KW_protected
| KW_pull0 | KW_pull0
| KW_pull1 | KW_pull1
| KW_pulldown | KW_pulldown
| KW_pullup | KW_pullup
| KW_pulsestyle_onevent | KW_pulsestyle_onevent
| KW_pulsestyle_ondetect | KW_pulsestyle_ondetect
| KW_pure | KW_pure
| KW_rand | KW_rand
| KW_randc | KW_randc
| KW_randcase | KW_randcase
| KW_randsequence | KW_randsequence
| KW_rcmos | KW_rcmos
| KW_real | KW_real
| KW_realtime | KW_realtime
| KW_ref | KW_ref
| KW_reg | KW_reg
| KW_release | KW_release
| KW_repeat | KW_repeat
| KW_return | KW_return
| KW_rnmos | KW_rnmos
| KW_rpmos | KW_rpmos
| KW_rtran | KW_rtran
| KW_rtranif0 | KW_rtranif0
| KW_rtranif1 | KW_rtranif1
| KW_scalared | KW_scalared
| KW_sequence | KW_sequence
| KW_shortint | KW_shortint
| KW_shortreal | KW_shortreal
| KW_showcancelled | KW_showcancelled
| KW_signed | KW_signed
| KW_small | KW_small
| KW_solve | KW_solve
| KW_specify | KW_specify
| KW_specparam | KW_specparam
| KW_static | KW_static
| KW_strength0 | KW_strength0
| KW_strength1 | KW_strength1
| KW_string | KW_string
| KW_strong0 | KW_strong0
| KW_strong1 | KW_strong1
| KW_struct | KW_struct
| KW_super | KW_super
| KW_supply0 | KW_supply0
| KW_supply1 | KW_supply1
| KW_table | KW_table
| KW_tagged | KW_tagged
| KW_task | KW_task
| KW_this | KW_this
| KW_throughout | KW_throughout
| KW_time | KW_time
| KW_timeprecision | KW_timeprecision
| KW_timeunit | KW_timeunit
| KW_tran | KW_tran
| KW_tranif0 | KW_tranif0
| KW_tranif1 | KW_tranif1
| KW_tri | KW_tri
| KW_tri0 | KW_tri0
| KW_tri1 | KW_tri1
| KW_triand | KW_triand
| KW_trior | KW_trior
| KW_trireg | KW_trireg
| KW_type | KW_type
| KW_typedef | KW_typedef
| KW_type_option | KW_type_option
| KW_union | KW_union
| KW_unique | KW_unique
| KW_unsigned | KW_unsigned
| KW_use | KW_use
| KW_var | KW_var
| KW_vectored | KW_vectored
| KW_virtual | KW_virtual
| KW_void | KW_void
| KW_wait | KW_wait
| KW_wait_order | KW_wait_order
| KW_wand | KW_wand
| KW_weak0 | KW_weak0
| KW_weak1 | KW_weak1
| KW_while | KW_while
| KW_wildcard | KW_wildcard
| KW_wire | KW_wire
| KW_with | KW_with
| KW_within | KW_within
| KW_wor | KW_wor
| KW_xnor | KW_xnor
| KW_xor | KW_xor
| Id_simple | Id_simple
| Id_escaped | Id_escaped
| Id_system | Id_system
......
Language/Verilog/Simulator.hs
...@@ -56,7 +56,7 @@ getSignalId netlist path = case lookup path paths' of ...@@ -56,7 +56,7 @@ getSignalId netlist path = case lookup path paths' of
Nothing -> Nothing Nothing -> Nothing
Just i -> Just $ Id i Just i -> Just $ Id i
where where
paths = [ (paths, id) | Reg id _ paths _ <- netlist ] ++ [ (paths, id) | Var id _ paths _ <- netlist ] paths = [ (paths, id) | Reg id _ paths _ <- netlist ] ++ [ (paths, id) | Var id _ paths _ <- netlist ]
paths' = [ (path, id) | (paths, id) <- paths, path <- paths ] paths' = [ (path, id) | (paths, id) <- paths, path <- paths ]
type Memory = IOArray Int BitVec type Memory = IOArray Int BitVec
...@@ -75,7 +75,7 @@ memory netlist ...@@ -75,7 +75,7 @@ memory netlist
initialize :: Netlist BlackBoxInit -> Memory -> IORef (Maybe VCDHandle) -> Maybe FilePath -> IORef (IO ()) -> IORef (IO ()) -> IO (Maybe SimResponse) initialize :: Netlist BlackBoxInit -> Memory -> IORef (Maybe VCDHandle) -> Maybe FilePath -> IORef (IO ()) -> IORef (IO ()) -> IO (Maybe SimResponse)
initialize netlist memory vcd file sample step = do initialize netlist memory vcd file sample step = do
close vcd sample step close vcd sample step
mapM_ (initializeNet memory) netlist mapM_ (initializeNet memory) netlist
case file of case file of
Nothing -> return () Nothing -> return ()
Just file -> do Just file -> do
......
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