hacky support for 'part-select addressing'

b45217ba · Zachary Snow · abd7ccf4 · b45217ba
Commit b45217ba authored Mar 30, 2019 by Zachary Snow
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src/Language/SystemVerilog/Parser/Parse.y
+4 -1

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--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -590,7 +590,10 @@ DeclAsgn :: { (Identifier, Expr) }
  : Identifier "=" Expr { ($1, $3) }
 Range :: { Range }
-  : "[" Expr ":" Expr "]"  { ($2, $4) }
+  : "[" Expr ":"  Expr "]" { ($2, $4) }
+  -- TODO: This assumes the ranges are always [hi:lo]; See section 11.5.1!
+  | "[" Expr "+:" Expr "]" { (BinOp Sub (BinOp Add $2 $4) (Number "1"), $2) }
+  | "[" Expr "-:" Expr "]" { ($2, BinOp Add (BinOp Sub $2 $4) (Number "1")) }
 LHS :: { LHS }
  : Identifier         { LHSIdent  $1    }