Commit b2b6f8f8 by Zachary Snow

fix two paramtype edge cases

- don't keep unused template modules even if they are fully-specified
- don't reduce modules with unbound type parameters
parent ab867465
......@@ -77,7 +77,7 @@ convert files =
|| isntTyped
|| isUsedAsUntyped
|| isUsedAsTyped && isInstantiatedViaNonTyped
|| allTypesHaveDefaults && notInstantiated
|| allTypesHaveDefaults && notInstantiated && isntTemplateTagged
where
maybeTypeMap = Map.lookup name modules
Just typeMap = maybeTypeMap
......@@ -88,6 +88,7 @@ convert files =
isInstantiatedViaNonTyped = untypedUsageSearch $ Set.singleton name
allTypesHaveDefaults = all (/= UnknownType) (Map.elems typeMap)
notInstantiated = lookup name instances == Nothing
isntTemplateTagged = not $ isTemplateTagged name
keepDescription _ = True
-- instantiate the type parameters if this is a used default instance
......@@ -99,6 +100,7 @@ convert files =
where
shouldntReduce =
Map.notMember name modules || Map.null typeMap ||
any (== UnknownType) (Map.elems typeMap) ||
isTemplateTagged name
typeMap = modules Map.! name
rewriteDecl :: Decl -> Decl
......
module mod1;
parameter type T = logic;
initial $display("%0d", $bits(T));
endmodule
module mod2;
parameter type T = logic;
typedef logic [$bits(T) - 1:0] A;
typedef logic [$bits(A) - 1:0] B;
mod1 #(A) mA();
mod1 #(B) mB();
endmodule
module mod3;
parameter type T = logic;
typedef logic [$bits(T) - 1:0] A;
typedef logic [$bits(A) - 1:0] B;
mod2 #(A) mA();
mod2 #(B) mB();
endmodule
module mod4;
parameter type T = logic;
typedef logic [$bits(T) - 1:0] A;
typedef logic [$bits(A) - 1:0] B;
mod3 #(A) mA();
mod3 #(B) mB();
endmodule
module top;
typedef struct packed { int a; } X;
typedef struct packed { int a; X b; } Y;
typedef logic [$bits(Y) - 1:0] A;
typedef logic [$bits(A) - 1:0] B;
mod4 #(A) m4A();
mod4 #(B) m4B();
endmodule
module top;
initial repeat (16) $display("%0d", 64);
endmodule
module leaf;
parameter type T = logic;
initial #1 $display("leaf: $bits(T)=%0d", $bits(T));
endmodule
module intermediate;
parameter type U = logic;
parameter W = 4;
parameter type S = logic [W - 1:0];
leaf #(S) l();
initial #2 $display("intermediate: $bits(U)=%0d W=%0d $bits(s)=%0d",
$bits(U), W, $bits(S));
endmodule
module top;
parameter type B = byte;
intermediate i1();
intermediate #(B) i2();
initial #3 $display("top: $bits(B)=%0d", $bits(B));
endmodule
module leaf;
parameter T = 1;
initial #1 $display("leaf: $bits(T)=%0d", T);
endmodule
module intermediate;
parameter U = 1;
parameter W = 4;
parameter S = W;
leaf #(S) l();
initial #2 $display("intermediate: $bits(U)=%0d W=%0d $bits(s)=%0d",
U, W, S);
endmodule
module top;
parameter B = 8;
intermediate i1();
intermediate #(B) i2();
initial #3 $display("top: $bits(B)=%0d", B);
endmodule
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