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lvzhengyang
sv2v
Commits
aea64e90
Commit
aea64e90
authored
Feb 13, 2020
by
Zachary Snow
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pack arrays assigned to other arrays
parent
104f9801
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3 changed files
with
22 additions
and
3 deletions
+22
-3
src/Convert/UnpackedArray.hs
+12
-3
test/basic/array.sv
+5
-0
test/basic/array.v
+5
-0
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src/Convert/UnpackedArray.hs
View file @
aea64e90
...
...
@@ -2,8 +2,8 @@
- Author: Zachary Snow <zach@zachjs.com>
-
- Conversion for any unpacked array which must be packed because it is: A) a
- port; B) is bound to a port;
or C) is assigned a value in a single
-
assignment
.
- port; B) is bound to a port;
C) is assigned a value in a single assignment;
-
or D) is assigned to an unpacked array which itself mus be packed
.
-
- The scoped nature of declarations makes this challenging. While scoping is
- obeyed in general, any of a set of *equivalent* declarations within a module
...
...
@@ -64,6 +64,7 @@ traverseModuleItemM item =
traverseModuleItemM'
item
>>=
traverseLHSsM
traverseLHSM
>>=
traverseExprsM
traverseExprM
>>=
traverseAsgnsM
traverseAsgnM
traverseModuleItemM'
::
ModuleItem
->
ST
ModuleItem
traverseModuleItemM'
(
Instance
a
b
c
d
bindings
)
=
do
...
...
@@ -80,7 +81,8 @@ traverseModuleItemM' other = return other
traverseStmtM
::
Stmt
->
ST
Stmt
traverseStmtM
stmt
=
traverseStmtLHSsM
traverseLHSM
stmt
>>=
traverseStmtExprsM
traverseExprM
traverseStmtExprsM
traverseExprM
>>=
traverseStmtAsgnsM
traverseAsgnM
traverseExprM
::
Expr
->
ST
Expr
traverseExprM
=
return
...
...
@@ -91,6 +93,13 @@ traverseLHSM (LHSIdent x) = do
return
$
LHSIdent
x
traverseLHSM
other
=
return
other
traverseAsgnM
::
(
LHS
,
Expr
)
->
ST
(
LHS
,
Expr
)
traverseAsgnM
(
LHSIdent
x
,
Ident
y
)
=
do
flatUsageM
x
flatUsageM
y
return
(
LHSIdent
x
,
Ident
y
)
traverseAsgnM
other
=
return
other
flatUsageM
::
Identifier
->
ST
()
flatUsageM
x
=
do
declMap
<-
get
...
...
test/basic/array.sv
0 → 100644
View file @
aea64e90
module
top
;
logic
[
1
:
0
]
a
[
3
]
;
logic
[
1
:
0
]
b
[
3
]
;
always_comb
a
=
b
;
endmodule
test/basic/array.v
0 → 100644
View file @
aea64e90
module
top
;
reg
[
5
:
0
]
a
;
wire
[
5
:
0
]
b
;
always
@
(
*
)
a
=
b
;
endmodule
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