Commit aa429204 by Zachary Snow

minor AlwaysKW coverage improvements

parent 3db3fc0c
...@@ -212,7 +212,6 @@ ports = filter ((/= Local) . snd) . map port ...@@ -212,7 +212,6 @@ ports = filter ((/= Local) . snd) . map port
port :: Decl -> PortDir port :: Decl -> PortDir
port (Variable d _ x _ _) = (x, d) port (Variable d _ x _ _) = (x, d)
port (Net d _ _ _ x _ _) = (x, d)
port _ = ("", Local) port _ = ("", Local)
-- get a list of non-local variables referenced within a module item, and -- get a list of non-local variables referenced within a module item, and
......
`include "always_sense.vh"
module mod( module mod(
input wire inp1, inp2, input wire `INPUTS,
output reg out1, out2, out3, out4, out5, out6, out7, out8, out9, outA, outB output reg `OUTPUTS
); );
localparam ZERO = 0; localparam ZERO = 0;
...@@ -75,4 +76,10 @@ module mod( ...@@ -75,4 +76,10 @@ module mod(
endfunction endfunction
always_comb always_comb
outB = h(ZERO); outB = h(ZERO);
function automatic i;
input reg x; // ignored
i = s[ONE];
endfunction
always_comb
asgn(.i(i(ZERO)), .o(outC));
endmodule endmodule
`include "always_sense.vh"
module mod( module mod(
input wire inp1, inp2, input wire `INPUTS,
output reg out1, out2, out3, out4, out5, out6, out7, out8, out9, outA, outB output reg `OUTPUTS
); );
localparam ZERO = 0; localparam ZERO = 0;
...@@ -73,4 +74,10 @@ module mod( ...@@ -73,4 +74,10 @@ module mod(
endfunction endfunction
always @(s[0]) always @(s[0])
outB = h(ZERO); outB = h(ZERO);
function automatic i;
input reg x; // ignored
i = s[1];
endfunction
always @(s[1])
asgn(outC, i(ZERO));
endmodule endmodule
`define INPUTS inp1, inp2
`define OUTPUTS out1, out2, out3, out4, out5, out6, out7, out8, out9, outA, outB, outC
`include "always_sense.vh"
module top; module top;
reg inp1, inp2; reg `INPUTS;
wire out1, out2, out3, out4, out5, out6, out7, out8, out9, outA, outB; wire `OUTPUTS;
mod m(inp1, inp2, out1, out2, out3, out4, out5, out6, out7, out8, out9, outA, outB); mod m(`INPUTS, `OUTPUTS);
initial begin initial begin
$monitor(inp1, inp2, $monitor(`INPUTS, `OUTPUTS);
out1, out2, out3, out4, out5, out6, out7, out8, out9, outA, outB);
repeat (2) begin repeat (2) begin
#1 inp1 = 0; #1 inp1 = 0;
#1 inp2 = 0; #1 inp2 = 0;
......
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