test suite iverilog 11.0 compatibility

test/basic/flatten.sv

@@ -6,15 +6,15 @@ module name(clock, in, out); \
     initial out[1+a] = 0; \
     initial out[2+a] = 0; \
     always @(posedge clock) begin \
-        $display($time, `" name @+ ", out[0+a][1+b+:1]); \
-        $display($time, `" name @+ ", out[1+a][1+b+:1]); \
-        $display($time, `" name @+ ", out[2+a][1+b+:1]); \
-        $display($time, `" name @+ ", out[0+a][1+b+:2]); \
-        $display($time, `" name @+ ", out[1+a][1+b+:2]); \
-        $display($time, `" name @+ ", out[2+a][1+b+:2]); \
-        $display($time, `" name @: ", out[0+a][1+b:1+b]); \
-        $display($time, `" name @: ", out[1+a][1+b:1+b]); \
-        $display($time, `" name @: ", out[2+a][1+b:1+b]); \
+        $display($time, `" name @+ `", out[0+a][1+b+:1]); \
+        $display($time, `" name @+ `", out[1+a][1+b+:1]); \
+        $display($time, `" name @+ `", out[2+a][1+b+:1]); \
+        $display($time, `" name @+ `", out[0+a][1+b+:2]); \
+        $display($time, `" name @+ `", out[1+a][1+b+:2]); \
+        $display($time, `" name @+ `", out[2+a][1+b+:2]); \
+        $display($time, `" name @: `", out[0+a][1+b:1+b]); \
+        $display($time, `" name @: `", out[1+a][1+b:1+b]); \
+        $display($time, `" name @: `", out[2+a][1+b:1+b]); \
  \
         out[2+a][4+b] = out[2+a][3+b]; \
         out[2+a][3+b] = out[2+a][2+b]; \

test/basic/flatten_tb.v

@@ -8,7 +8,7 @@
     initial begin \
         for (tag``i = 0; tag``i < 20; tag``i++) begin \
             #2; \
-            $display(`"tag", $time, ": %h %15b %15b %15b %15b", in, \
+            $display(`"tag`", $time, ": %h %15b %15b %15b %15b", in, \
                 tag``one_out, tag``two_out, tag``thr_out, tag``fou_out); \
         end \
     end

test/basic/flatten_three_tb.v

@@ -8,7 +8,7 @@
     initial begin \
         for (tag``i = 0; tag``i < 40; tag``i++) begin \
             #2; \
-            $display(`"tag", $time, ": %h %30b %30b %30b %30b", in, \
+            $display(`"tag`", $time, ": %h %30b %30b %30b %30b", in, \
                 tag``one_out, tag``two_out, tag``thr_out, tag``fou_out); \
         end \
     end

test/basic/unsigned.sv

 module top;
     logic [3:0] arr;
-    always_comb
+    initial
         for (int unsigned i = 0; i < 4; i++)
             arr[i] = i;
     initial $display(arr);

test/basic/unsigned.v

 module top;
     reg [3:0] arr;
-    always @* begin : block_name
+    initial begin : block_name
         integer i;
         for (i = 0; i < 4; i++)
             arr[i] = i;

test/lex/macro_iv.sv

@@ -116,7 +116,7 @@
 
 /* removed MACRO_E because iverlog performs escaping withing normal quotes */
 
-`define MACRO_F(t) $display(`"s t = `\`"t`\`"");
+`define MACRO_F(t) $display(`"s t = `\`"t`\`"`");
 
 module top;
 initial begin