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lvzhengyang
sv2v
Commits
a5ebb1e8
Commit
a5ebb1e8
authored
Apr 18, 2019
by
Zachary Snow
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minor output cleanup
parent
4cbfd8fa
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2 changed files
with
5 additions
and
2 deletions
+5
-2
src/Convert/Enum.hs
+4
-1
src/Language/SystemVerilog/AST/Type.hs
+1
-1
No files found.
src/Convert/Enum.hs
View file @
a5ebb1e8
...
...
@@ -67,10 +67,13 @@ traverseType :: Type -> Writer Enums Type
traverseType
(
Enum
t
v
rs
)
=
do
let
baseType
=
toBaseType
t
let
(
tf
,
r
)
=
typeRanges
baseType
()
<-
tell
$
Set
.
singleton
(
r
,
v
)
()
<-
tell
$
Set
.
singleton
(
map
simplifyRange
r
,
v
)
return
$
tf
(
r
++
rs
)
traverseType
other
=
return
other
simplifyRange
::
Range
->
Range
simplifyRange
(
a
,
b
)
=
(
simplify
a
,
simplify
b
)
-- drop any enum type casts in favor of implicit conversion from the
-- converted type
traverseExpr
::
Expr
->
Expr
...
...
src/Language/SystemVerilog/AST/Type.hs
View file @
a5ebb1e8
...
...
@@ -43,7 +43,7 @@ data Type
instance
Show
Type
where
show
(
Alias
xx
rs
)
=
printf
"%s%s"
xx
(
showRanges
rs
)
show
(
Net
kw
rs
)
=
printf
"%s%s"
(
show
kw
)
(
showRanges
rs
)
show
(
Implicit
sg
rs
)
=
printf
"%s%s"
(
show
sg
)
(
showRanges
rs
)
show
(
Implicit
sg
rs
)
=
printf
"%s%s"
(
show
Pad
sg
)
(
dropWhile
(
==
' '
)
$
showRanges
rs
)
show
(
IntegerVector
kw
sg
rs
)
=
printf
"%s%s%s"
(
show
kw
)
(
showPadBefore
sg
)
(
showRanges
rs
)
show
(
IntegerAtom
kw
sg
)
=
printf
"%s%s"
(
show
kw
)
(
showPadBefore
sg
)
show
(
NonInteger
kw
)
=
printf
"%s"
(
show
kw
)
...
...
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