Commit a54be8da by Zachary Snow

instances supply names during reordering

parent 59b416f9
......@@ -38,6 +38,7 @@
accessed directly
* Fixed conversion of casts using structs containing multi-dimensional fields
* Fixed incorrect name resolution conflicts raised during interface inlining
* Fixed handling of interface instances which shadow other declarations
## v0.0.9
......
......@@ -652,7 +652,7 @@ reorderGenItem item = item
-- iteratively inserts missing package items exactly where they are needed
addItems :: PIs -> Idents -> [(ModuleItem, Idents)] -> [ModuleItem]
addItems pis existingPIs ((item, usedPIs) : items) =
if not $ Set.disjoint existingPIs thisPI then
if not $ forceKeep || Set.disjoint existingPIs thisPI then
-- this item was re-imported earlier in the module
addItems pis existingPIs items
else if Map.null itemsToAdd then
......@@ -666,7 +666,11 @@ addItems pis existingPIs ((item, usedPIs) : items) =
thisPI = case item of
MIPackageItem packageItem ->
Set.fromList $ piNames packageItem
Instance _ _ x _ _ -> Set.singleton x
_ -> Set.empty
forceKeep = case item of
Instance{} -> True
_ -> False
neededPIs = Set.difference (Set.difference usedPIs existingPIs) thisPI
itemsToAdd = Map.restrictKeys pis neededPIs
(chosenName, chosenPI) = Map.findMin itemsToAdd
......
typedef logic over;
interface intf;
logic [3:0] x;
assign x[0] = 0;
initial $display("intf x %b", x);
endinterface
module mod(intf i);
assign i.x[1] = 1;
initial $display("mod i.x %b", i.x);
endmodule
module check;
over y;
intf over();
mod m(over);
assign over.x[2] = 1'bz;
initial $display("check over.x %b", over.x);
initial $display("check y %b", y);
endmodule
module top;
check c();
intf over();
mod m(over);
assign over.x[2] = 1'bz;
initial $display("top over.x %b", over.x);
endmodule
module check;
wire y;
if (1) begin : over
wire [3:0] x;
assign x[0] = 0;
initial $display("intf x %b", x);
end
if (1) begin : m
assign over.x[1] = 1;
initial $display("mod i.x %b", over.x);
end
assign over.x[2] = 1'bz;
initial $display("check over.x %b", over.x);
initial $display("check y %b", y);
endmodule
module top;
check c();
if (1) begin : over
wire [3:0] x;
assign x[0] = 0;
initial $display("intf x %b", x);
end
if (1) begin : m
assign over.x[1] = 1;
initial $display("mod i.x %b", over.x);
end
assign over.x[2] = 1'bz;
initial $display("top over.x %b", over.x);
endmodule
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