additional SystemVerilog language support

- unique0 and priority
- uniqueness on if statements
- preliminary discard-only parsing of assertions
- parameters with alias typenames

src/Convert/Traverse.hs

@@ -150,10 +150,10 @@ traverseNestedStmtsM mapper = fullMapper
         cs (RepeatL e stmt) = fullMapper stmt >>= return . RepeatL e
         cs (DoWhile e stmt) = fullMapper stmt >>= return . DoWhile e
         cs (Forever   stmt) = fullMapper stmt >>= return . Forever
-        cs (If e s1 s2) = do
+        cs (If u e s1 s2) = do
             s1' <- fullMapper s1
             s2' <- fullMapper s2
-            return $ If e s1' s2'
+            return $ If u e s1' s2'
         cs (Timing event stmt) = fullMapper stmt >>= return . Timing event
         cs (Return expr) = return $ Return expr
         cs (Subroutine f exprs) = return $ Subroutine f exprs
@@ -294,8 +294,8 @@ traverseExprsM mapper = moduleItemMapper
     flatStmtMapper (DoWhile e stmt) =
         exprMapper e >>= \e' -> return $ DoWhile e' stmt
     flatStmtMapper (Forever   stmt) = return $ Forever stmt
-    flatStmtMapper (If cc s1 s2) =
-        exprMapper cc >>= \cc' -> return $ If cc' s1 s2
+    flatStmtMapper (If u cc s1 s2) =
+        exprMapper cc >>= \cc' -> return $ If u cc' s1 s2
     flatStmtMapper (Timing event stmt) = return $ Timing event stmt
     flatStmtMapper (Subroutine f exprs) =
         mapM maybeExprMapper exprs >>= return . Subroutine f

src/Convert/Unique.hs

 {- sv2v
  - Author: Zachary Snow <zach@zachjs.com>
  -
- - Conversion for `unique`
+ - Conversion for `unique`, `unique0`, and `priority`
  -
- - This conversion simply drops the `unique` keyword, as it is only used for
+ - This conversion simply drops the keywords, as it is only used for
  - optimization. There is no way to force toolchains which don't support the
  - keyword to perform such optimization.
  -}
@@ -17,6 +17,8 @@ convert :: AST -> AST
 convert = traverseDescriptions $ traverseModuleItems $ traverseStmts convertStmt
 
 convertStmt :: Stmt -> Stmt
-convertStmt (Case True kw expr cases def) =
-    Case False kw expr cases def
+convertStmt (If (Just _) cc s1 s2) =
+    If Nothing cc s1 s2
+convertStmt (Case (Just _) kw expr cases def) =
+    Case Nothing kw expr cases def
 convertStmt other = other

src/Language/SystemVerilog/AST.hs

@@ -128,6 +128,8 @@ data ModuleItem
   | MIPackageItem PackageItem
   | NInputGate  NInputGateKW  (Maybe Identifier)  LHS [Expr]
   | NOutputGate NOutputGateKW (Maybe Identifier) [LHS] Expr
+  -- TODO: Should we support coversion of assertions?
+  -- | AssertionItem AssertionItem
   deriving Eq
 
 data AlwaysKW
@@ -165,6 +167,7 @@ instance Show ModuleItem where
     MIPackageItem i  -> show i
     NInputGate  kw x lhs  exprs -> printf "%s%s (%s, %s);" (show kw) (maybe "" (" " ++) x) (show lhs) (commas $ map show exprs)
     NOutputGate kw x lhss expr  -> printf "%s%s (%s, %s);" (show kw) (maybe "" (" " ++) x) (commas $ map show lhss) (show expr)
+    --AssertionItem a -> show a
     where
     showPorts :: [PortBinding] -> String
     showPorts ports = indentedParenList $ map showPort ports

src/Language/SystemVerilog/AST/Stmt.hs

@@ -11,6 +11,15 @@ module Language.SystemVerilog.AST.Stmt
     , Sense  (..)
     , CaseKW (..)
     , Case
+    , ActionBlock  (..)
+    , PropertyExpr (..)
+    , PESPBinOp    (..)
+    , SeqMatchItem
+    , SeqExpr      (..)
+    , AssertionItem
+    , Assertion    (..)
+    , PropertySpec (..)
+    , UniquePriority (..)
     ) where
 
 import Text.Printf (printf)
@@ -26,7 +35,7 @@ import Language.SystemVerilog.AST.Type (Identifier)
 data Stmt
     = StmtAttr Attr Stmt
     | Block   (Maybe Identifier) [Decl] [Stmt]
-    | Case    Bool CaseKW Expr [Case] (Maybe Stmt)
+    | Case    (Maybe UniquePriority) CaseKW Expr [Case] (Maybe Stmt)
     | For     [Either Decl (LHS, Expr)] (Maybe Expr) [(LHS, AsgnOp, Expr)] Stmt
     | AsgnBlk AsgnOp LHS Expr
     | Asgn    (Maybe Timing) LHS Expr
@@ -34,11 +43,13 @@ data Stmt
     | RepeatL Expr Stmt
     | DoWhile Expr Stmt
     | Forever Stmt
-    | If      Expr Stmt Stmt
+    | If      (Maybe UniquePriority) Expr Stmt Stmt
     | Timing  Timing Stmt
     | Return  Expr
     | Subroutine Identifier [Maybe Expr]
     | Trigger Identifier
+    -- TODO: Should we support coversion of assertions?
+    -- | Assertion Assertion
     | Null
     deriving Eq
 
@@ -51,9 +62,8 @@ instance Show Stmt where
             bodyLines = (map show decls) ++ (map show stmts)
             body = indent $ unlines' bodyLines
     show (Case u kw e cs def) =
-        printf "%s%s (%s)\n%s%s\nendcase" uniqStr (show kw) (show e) bodyStr defStr
+        printf "%s%s (%s)\n%s%s\nendcase" (maybe "" showPad u) (show kw) (show e) bodyStr defStr
         where
-            uniqStr = if u then "unique " else ""
             bodyStr = indent $ unlines' $ map showCase cs
             defStr = case def of
                 Nothing -> ""
@@ -77,11 +87,12 @@ instance Show Stmt where
     show (RepeatL e s) = printf "repeat (%s) %s" (show e) (show s)
     show (DoWhile e s) = printf "do %s while (%s);" (show s) (show e)
     show (Forever s  ) = printf "forever %s" (show s)
-    show (If a b Null) = printf "if (%s) %s"         (show a) (show b)
-    show (If a b c   ) = printf "if (%s) %s\nelse %s" (show a) (show b) (show c)
+    show (If u a b Null) = printf "%sif (%s) %s"          (maybe "" showPad u) (show a) (show b)
+    show (If u a b c   ) = printf "%sif (%s) %s\nelse %s" (maybe "" showPad u) (show a) (show b) (show c)
     show (Return e   ) = printf "return %s;" (show e)
     show (Timing t s ) = printf "%s %s" (show t) (show s)
     show (Trigger x  ) = printf "-> %s;" x
+    --show (Assertion a) = show a
     show (Null       ) = ";"
 
 data CaseKW
@@ -122,3 +133,85 @@ instance Show Sense where
     show (SensePosedge a  ) = printf "posedge %s" (show a)
     show (SenseNegedge a  ) = printf "negedge %s" (show a)
     show (SenseStar       ) = "*"
+
+data ActionBlock
+    = ActionBlockIf   Stmt
+    | ActionBlockElse (Maybe Stmt) Stmt
+    deriving Eq
+instance Show ActionBlock where
+    show (ActionBlockIf   Null        ) = ";"
+    show (ActionBlockIf   s           ) = printf " %s" (show s)
+    show (ActionBlockElse Nothing   s ) = printf " else %s" (show s)
+    show (ActionBlockElse (Just s1) s2) = printf " %s else %s" (show s1) (show s2)
+
+data PropertyExpr
+    = PESE SeqExpr
+    | PESPBinOp SeqExpr PESPBinOp PropertyExpr
+    deriving Eq
+instance Show PropertyExpr where
+    show (PESE se) = show se
+    show (PESPBinOp a o b) = printf "(%s %s %s)" (show a) (show o) (show b)
+data PESPBinOp
+    = ImpliesO
+    | ImpliesNO
+    | FollowedByO
+    | FollowedByNO
+    deriving (Eq, Ord)
+instance Show PESPBinOp where
+    show ImpliesO     = "|->"
+    show ImpliesNO    = "|=>"
+    show FollowedByO  = "#-#"
+    show FollowedByNO = "#=#"
+type SeqMatchItem = Either (LHS, AsgnOp, Expr) (Identifier, [Maybe Expr])
+data SeqExpr
+    = SeqExpr Expr
+    | SeqExprAnd        SeqExpr SeqExpr
+    | SeqExprOr         SeqExpr SeqExpr
+    | SeqExprIntersect  SeqExpr SeqExpr
+    | SeqExprThroughout Expr    SeqExpr
+    | SeqExprWithin     SeqExpr SeqExpr
+    | SeqExprDelay (Maybe SeqExpr) Expr SeqExpr
+    | SeqExprFirstMatch SeqExpr [SeqMatchItem]
+    deriving Eq
+instance Show SeqExpr where
+    show (SeqExpr           a  ) = show a
+    show (SeqExprAnd        a b) = printf "(%s %s %s)" (show a) "and"        (show b)
+    show (SeqExprOr         a b) = printf "(%s %s %s)" (show a) "or"         (show b)
+    show (SeqExprIntersect  a b) = printf "(%s %s %s)" (show a) "intersect"  (show b)
+    show (SeqExprThroughout a b) = printf "(%s %s %s)" (show a) "throughout" (show b)
+    show (SeqExprWithin     a b) = printf "(%s %s %s)" (show a) "within"     (show b)
+    show (SeqExprDelay   me e s) = printf "%s##%s %s" (maybe "" showPad me) (show e) (show s)
+    show (SeqExprFirstMatch e l) = printf "first_match(%s, %s)" (show e) (commas $ map show l)
+
+type AssertionItem = (Maybe Identifier, Assertion)
+data Assertion
+    = Assert         Expr         ActionBlock
+    | AssertProperty PropertySpec ActionBlock
+    deriving Eq
+instance Show Assertion where
+    show (Assert e a) =
+        printf "assert (%s)%s" (show e) (show a)
+    show (AssertProperty p a) =
+        printf "assert property (%s)%s" (show p) (show a)
+
+data PropertySpec
+    = PropertySpec (Maybe Sense) (Maybe Expr) PropertyExpr
+    deriving Eq
+instance Show PropertySpec where
+    show (PropertySpec ms me pe) =
+        printf "%s%s%s" (maybe "" showPad ms) meStr (show pe)
+        where
+            meStr = case me of
+                Nothing -> ""
+                Just e -> printf "disable iff (%s) " (show e)
+
+data UniquePriority
+    = Unique
+    | Unique0
+    | Priority
+    deriving Eq
+
+instance Show UniquePriority where
+    show Unique   = "unique"
+    show Unique0  = "unique0"
+    show Priority = "priority"

src/Language/SystemVerilog/Parser/Lex.x

@@ -107,6 +107,7 @@ tokens :-
     "always_ff"        { tok KW_always_ff    }
     "always_latch"     { tok KW_always_latch }
     "and"              { tok KW_and          }
+    "assert"           { tok KW_assert       }
     "assign"           { tok KW_assign       }
     "automatic"        { tok KW_automatic    }
     "begin"            { tok KW_begin        }
@@ -118,6 +119,7 @@ tokens :-
     "casez"            { tok KW_casez        }
     "default"          { tok KW_default      }
     "defparam"         { tok KW_defparam     }
+    "disable"          { tok KW_disable      }
     "do"               { tok KW_do           }
     "else"             { tok KW_else         }
     "end"              { tok KW_end          }
@@ -129,18 +131,21 @@ tokens :-
     "endtask"          { tok KW_endtask      }
     "enum"             { tok KW_enum         }
     "extern"           { tok KW_extern       }
+    "first_match"      { tok KW_first_match  }
     "for"              { tok KW_for          }
     "forever"          { tok KW_forever      }
     "function"         { tok KW_function     }
     "generate"         { tok KW_generate     }
     "genvar"           { tok KW_genvar       }
     "if"               { tok KW_if           }
+    "iff"              { tok KW_iff          }
     "initial"          { tok KW_initial      }
     "inout"            { tok KW_inout        }
     "input"            { tok KW_input        }
     "int"              { tok KW_int          }
     "integer"          { tok KW_integer      }
     "interface"        { tok KW_interface    }
+    "intersect"        { tok KW_intersect    }
     "localparam"       { tok KW_localparam   }
     "logic"            { tok KW_logic        }
     "longint"          { tok KW_longint      }
@@ -155,6 +160,8 @@ tokens :-
     "packed"           { tok KW_packed       }
     "parameter"        { tok KW_parameter    }
     "posedge"          { tok KW_posedge      }
+    "priority"         { tok KW_priority     }
+    "property"         { tok KW_property     }
     "real"             { tok KW_real         }
     "realtime"         { tok KW_realtime     }
     "reg"              { tok KW_reg          }
@@ -168,6 +175,7 @@ tokens :-
     "supply0"          { tok KW_supply0      }
     "supply1"          { tok KW_supply1      }
     "task"             { tok KW_task         }
+    "throughout"       { tok KW_throughout   }
     "time"             { tok KW_time         }
     "tri"              { tok KW_tri          }
     "tri0"             { tok KW_tri0         }
@@ -177,11 +185,13 @@ tokens :-
     "trireg"           { tok KW_trireg       }
     "typedef"          { tok KW_typedef      }
     "unique"           { tok KW_unique       }
+    "unique0"          { tok KW_unique0      }
     "unsigned"         { tok KW_unsigned     }
     "uwire"            { tok KW_uwire        }
     "wand"             { tok KW_wand         }
     "while"            { tok KW_while        }
     "wire"             { tok KW_wire         }
+    "within"           { tok KW_within       }
     "wor"              { tok KW_wor          }
     "xnor"             { tok KW_xnor         }
     "xor"              { tok KW_xor          }
@@ -272,6 +282,8 @@ tokens :-
     "|->"              { tok Sym_bar_dash_gt }
     "|=>"              { tok Sym_bar_eq_gt }
     "[->"              { tok Sym_brack_l_dash_gt }
+    "#-#"              { tok Sym_pound_dash_pound }
+    "#=#"              { tok Sym_pound_eq_pound }
     "@@("              { tok Sym_at_at_paren_l }
     "(*)"              { tok Sym_paren_l_aster_paren_r }
     "->>"              { tok Sym_dash_gt_gt }

src/Language/SystemVerilog/Parser/Tokens.hs

@@ -225,6 +225,7 @@ data TokenName
   | KW_type_option
   | KW_union
   | KW_unique
+  | KW_unique0
   | KW_unsigned
   | KW_use
   | KW_uwire
@@ -327,6 +328,8 @@ data TokenName
   | Sym_gt_gt_eq
   | Sym_bar_dash_gt
   | Sym_bar_eq_gt
+  | Sym_pound_dash_pound
+  | Sym_pound_eq_pound
   | Sym_brack_l_dash_gt
   | Sym_at_at_paren_l
   | Sym_paren_l_aster_paren_r