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lvzhengyang
sv2v
Commits
a14d0782
Commit
a14d0782
authored
Sep 11, 2019
by
Zachary Snow
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substitution conversion for size casts (closes #27)
parent
6ddf7823
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9 changed files
with
39 additions
and
19 deletions
+39
-19
src/Convert.hs
+2
-2
src/Convert/Enum.hs
+1
-1
src/Convert/Simplify.hs
+17
-10
src/Convert/Typedef.hs
+1
-0
src/Language/SystemVerilog/AST/Expr.hs
+3
-3
src/Language/SystemVerilog/Parser/Parse.y
+2
-2
sv2v.cabal
+1
-1
test/basic/size_cast.sv
+6
-0
test/basic/size_cast.v
+6
-0
No files found.
src/Convert.hs
View file @
a14d0782
...
@@ -22,7 +22,6 @@ import qualified Convert.Interface
...
@@ -22,7 +22,6 @@ import qualified Convert.Interface
import
qualified
Convert.IntTypes
import
qualified
Convert.IntTypes
import
qualified
Convert.KWArgs
import
qualified
Convert.KWArgs
import
qualified
Convert.Logic
import
qualified
Convert.Logic
import
qualified
Convert.Mux
import
qualified
Convert.NamedBlock
import
qualified
Convert.NamedBlock
import
qualified
Convert.NestPI
import
qualified
Convert.NestPI
import
qualified
Convert.Package
import
qualified
Convert.Package
...
@@ -30,6 +29,7 @@ import qualified Convert.PackedArray
...
@@ -30,6 +29,7 @@ import qualified Convert.PackedArray
import
qualified
Convert.ParamType
import
qualified
Convert.ParamType
import
qualified
Convert.RemoveComments
import
qualified
Convert.RemoveComments
import
qualified
Convert.Return
import
qualified
Convert.Return
import
qualified
Convert.Simplify
import
qualified
Convert.StarPort
import
qualified
Convert.StarPort
import
qualified
Convert.StmtBlock
import
qualified
Convert.StmtBlock
import
qualified
Convert.Stream
import
qualified
Convert.Stream
...
@@ -53,9 +53,9 @@ phases excludes =
...
@@ -53,9 +53,9 @@ phases excludes =
,
Convert
.
EmptyArgs
.
convert
,
Convert
.
EmptyArgs
.
convert
,
Convert
.
IntTypes
.
convert
,
Convert
.
IntTypes
.
convert
,
Convert
.
KWArgs
.
convert
,
Convert
.
KWArgs
.
convert
,
Convert
.
Mux
.
convert
,
Convert
.
PackedArray
.
convert
,
Convert
.
PackedArray
.
convert
,
Convert
.
ParamType
.
convert
,
Convert
.
ParamType
.
convert
,
Convert
.
Simplify
.
convert
,
Convert
.
StarPort
.
convert
,
Convert
.
StarPort
.
convert
,
Convert
.
StmtBlock
.
convert
,
Convert
.
StmtBlock
.
convert
,
Convert
.
Stream
.
convert
,
Convert
.
Stream
.
convert
...
...
src/Convert/Enum.hs
View file @
a14d0782
...
@@ -95,7 +95,7 @@ toItem ((mr, x), v) =
...
@@ -95,7 +95,7 @@ toItem ((mr, x), v) =
where
where
v'
=
if
mr
==
Nothing
v'
=
if
mr
==
Nothing
then
simplify
v
then
simplify
v
else
sizedExpr
x
r
(
simplify
v
)
else
sizedExpr
x
(
rangeSize
r
)
(
simplify
v
)
rs
=
maybe
[]
(
\
a
->
[
a
])
mr
rs
=
maybe
[]
(
\
a
->
[
a
])
mr
r
=
defaultRange
mr
r
=
defaultRange
mr
itemType
=
Implicit
Unspecified
rs
itemType
=
Implicit
Unspecified
rs
...
...
src/Convert/
Mux
.hs
→
src/Convert/
Simplify
.hs
View file @
a14d0782
{- sv2v
{- sv2v
- Author: Zachary Snow <zach@zachjs.com>
- Author: Zachary Snow <zach@zachjs.com>
-
-
- Elaboration of
ternary expressions where the condition references a
- Elaboration of
size casts and ternary expressions where the condition
- localparam.
-
references a
localparam.
-
-
- Our conversions generate a lot of ternary expressions. This conversion
- Our conversions generate a lot of ternary expressions. This conversion
- attempts to make the code output a bit cleaner. Note that we can only do this
- attempts to make the code output a bit cleaner. Note that we can only do this
...
@@ -14,7 +14,7 @@
...
@@ -14,7 +14,7 @@
- expression to be simplified further.
- expression to be simplified further.
-}
-}
module
Convert.
Mux
(
convert
)
where
module
Convert.
Simplify
(
convert
)
where
import
Control.Monad.State
import
Control.Monad.State
import
qualified
Data.Map.Strict
as
Map
import
qualified
Data.Map.Strict
as
Map
...
@@ -48,18 +48,25 @@ traverseExprM :: Expr -> State Info Expr
...
@@ -48,18 +48,25 @@ traverseExprM :: Expr -> State Info Expr
traverseExprM
=
traverseNestedExprsM
$
stately
convertExpr
traverseExprM
=
traverseNestedExprsM
$
stately
convertExpr
convertExpr
::
Info
->
Expr
->
Expr
convertExpr
::
Info
->
Expr
->
Expr
convertExpr
info
(
Cast
(
Right
c
)
e
)
=
if
sized
==
e
then
Cast
(
Right
c'
)
e
else
sized
where
c'
=
simplify
$
traverseNestedExprs
(
substitute
info
)
(
simplify
c
)
sized
=
sizedExpr
""
c'
e
convertExpr
info
(
Mux
cc
aa
bb
)
=
convertExpr
info
(
Mux
cc
aa
bb
)
=
if
before
==
after
if
before
==
after
then
Mux
cc
aa
bb
then
Mux
cc
aa
bb
else
simplify
$
Mux
after
aa
bb
else
simplify
$
Mux
after
aa
bb
where
where
before
=
traverseNestedExprs
substitute
(
simplify
cc
)
before
=
traverseNestedExprs
(
substitute
info
)
(
simplify
cc
)
after
=
simplify
before
after
=
simplify
before
substitute
::
Expr
->
Expr
substitute
(
Ident
x
)
=
case
Map
.
lookup
x
info
of
Nothing
->
Ident
x
Just
e
->
e
substitute
other
=
other
convertExpr
_
other
=
other
convertExpr
_
other
=
other
substitute
::
Info
->
Expr
->
Expr
substitute
info
(
Ident
x
)
=
case
Map
.
lookup
x
info
of
Nothing
->
Ident
x
Just
e
->
e
substitute
_
other
=
other
src/Convert/Typedef.hs
View file @
a14d0782
...
@@ -57,6 +57,7 @@ convertDescription globalTypes description =
...
@@ -57,6 +57,7 @@ convertDescription globalTypes description =
else
Right
$
Ident
x
else
Right
$
Ident
x
convertTypeOrExpr
other
=
other
convertTypeOrExpr
other
=
other
convertExpr
::
Expr
->
Expr
convertExpr
::
Expr
->
Expr
convertExpr
(
Cast
v
e
)
=
Cast
(
convertTypeOrExpr
v
)
e
convertExpr
(
Bits
v
)
=
Bits
$
convertTypeOrExpr
v
convertExpr
(
Bits
v
)
=
Bits
$
convertTypeOrExpr
v
convertExpr
other
=
other
convertExpr
other
=
other
convertModuleItem
::
ModuleItem
->
ModuleItem
convertModuleItem
::
ModuleItem
->
ModuleItem
...
...
src/Language/SystemVerilog/AST/Expr.hs
View file @
a14d0782
...
@@ -217,14 +217,14 @@ endianCondRange r r1 r2 =
...
@@ -217,14 +217,14 @@ endianCondRange r r1 r2 =
)
)
-- attempts to make a number literal have an explicit size
-- attempts to make a number literal have an explicit size
sizedExpr
::
Identifier
->
Range
->
Expr
->
Expr
sizedExpr
::
Identifier
->
Expr
->
Expr
->
Expr
sizedExpr
x
r
(
Number
n
)
=
sizedExpr
x
s
(
Number
n
)
=
if
size
/=
show
resSize
if
size
/=
show
resSize
then
error
$
"literal "
++
show
n
++
" for "
++
show
x
then
error
$
"literal "
++
show
n
++
" for "
++
show
x
++
" doesn't have size "
++
show
size
++
" doesn't have size "
++
show
size
else
Number
res
else
Number
res
where
where
Number
size
=
simplify
$
rangeSize
r
Number
size
=
simplify
s
unticked
=
case
n
of
unticked
=
case
n
of
'
\'
'
:
rest
->
rest
'
\'
'
:
rest
->
rest
rest
->
rest
rest
->
rest
...
...
src/Language/SystemVerilog/Parser/Parse.y
View file @
a14d0782
...
@@ -1021,8 +1021,8 @@ Expr :: { Expr }
...
@@ -1021,8 +1021,8 @@ Expr :: { Expr }
| Expr "?" Expr ":" Expr { Mux $1 $3 $5 }
| Expr "?" Expr ":" Expr { Mux $1 $3 $5 }
| CastingType "'" "(" Expr ")" { Cast (Left $1) $4 }
| CastingType "'" "(" Expr ")" { Cast (Left $1) $4 }
| Number "'" "(" Expr ")" { Cast (Right $ Number $1) $4 }
| Number "'" "(" Expr ")" { Cast (Right $ Number $1) $4 }
| Identifier "'" "(" Expr ")" { Cast (
Left $ Alias (Nothing) $1 []
) $4 }
| Identifier "'" "(" Expr ")" { Cast (
Right $ Ident $1
) $4 }
| Identifier "::" Identifier "'" "(" Expr ")" { Cast (
Left $ Alias (Just $1) $3 []
) $6 }
| Identifier "::" Identifier "'" "(" Expr ")" { Cast (
Right $ PSIdent $1 $3
) $6 }
| Expr "." Identifier { Dot $1 $3 }
| Expr "." Identifier { Dot $1 $3 }
| "'" "{" PatternItems "}" { Pattern $3 }
| "'" "{" PatternItems "}" { Pattern $3 }
| "{" StreamOp StreamSize Concat "}" { Stream $2 $3 $4 }
| "{" StreamOp StreamSize Concat "}" { Stream $2 $3 $4 }
...
...
sv2v.cabal
View file @
a14d0782
...
@@ -66,7 +66,6 @@ executable sv2v
...
@@ -66,7 +66,6 @@ executable sv2v
Convert.IntTypes
Convert.IntTypes
Convert.KWArgs
Convert.KWArgs
Convert.Logic
Convert.Logic
Convert.Mux
Convert.NamedBlock
Convert.NamedBlock
Convert.NestPI
Convert.NestPI
Convert.Package
Convert.Package
...
@@ -74,6 +73,7 @@ executable sv2v
...
@@ -74,6 +73,7 @@ executable sv2v
Convert.ParamType
Convert.ParamType
Convert.RemoveComments
Convert.RemoveComments
Convert.Return
Convert.Return
Convert.Simplify
Convert.StarPort
Convert.StarPort
Convert.StmtBlock
Convert.StmtBlock
Convert.Stream
Convert.Stream
...
...
test/basic/size_cast.sv
0 → 100644
View file @
a14d0782
module
top
;
localparam
BW
=
3
;
logic
[
2
:
0
]
test
;
assign
test
=
BW
'
(
0
)
;
initial
$
display
(
test
)
;
endmodule
test/basic/size_cast.v
0 → 100644
View file @
a14d0782
module
top
;
localparam
BW
=
3
;
wire
[
2
:
0
]
test
;
assign
test
=
0
;
initial
$
display
(
test
)
;
endmodule
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