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lvzhengyang
sv2v
Commits
9c160c3d
Commit
9c160c3d
authored
Aug 03, 2019
by
Zachary Snow
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added support for package imports in module headers
parent
35ac09aa
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3 changed files
with
25 additions
and
2 deletions
+25
-2
src/Language/SystemVerilog/Parser/Parse.y
+9
-2
test/basic/header_import.sv
+10
-0
test/basic/header_import.v
+6
-0
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src/Language/SystemVerilog/Parser/Parse.y
View file @
9c160c3d
...
...
@@ -336,8 +336,8 @@ Packing :: { Packing }
| {- empty -} { Unpacked }
Part(begin, end) :: { Description }
: begin opt(Lifetime) Identifier Pa
rams PortDecls ";" ModuleItems end opt(Tag) { Part False $1 $2 $3 (fst $5) ($4 ++ (snd $5) ++ $7
) }
| "extern" begin opt(Lifetime) Identifier Pa
rams PortDecls ";" { Part True $2 $3 $4 (fst $6) ($5 ++ (snd $6
) ) }
: begin opt(Lifetime) Identifier Pa
ckageImportDeclarations Params PortDecls ";" ModuleItems end opt(Tag) { Part False $1 $2 $3 (fst $6) ($4 ++ $5 ++ (snd $6) ++ $8
) }
| "extern" begin opt(Lifetime) Identifier Pa
ckageImportDeclarations Params PortDecls ";" { Part True $2 $3 $4 (fst $7) ($5 ++ $6 ++ (snd $7
) ) }
ModuleKW :: { PartKW }
: "module" { Module }
...
...
@@ -350,6 +350,13 @@ PackageDeclaration :: { Description }
Tag :: { Identifier }
: ":" Identifier { $2 }
PackageImportDeclarations :: { [ModuleItem] }
: PackageImportDeclaration PackageImportDeclarations { $1 ++ $2 }
| {- empty -} { [] }
PackageImportDeclaration :: { [ModuleItem] }
: "import" PackageImportItems ";" { map (MIPackageItem . uncurry Import) $2 }
Params :: { [ModuleItem] }
: {- empty -} { [] }
| "#" "(" ParamDecls { $3 }
...
...
test/basic/header_import.sv
0 → 100644
View file @
9c160c3d
package
P
;
localparam
FOO
=
10
;
endpackage
module
top
import
P
::
FOO
;
;
initial
begin
$
display
(
FOO
)
;
end
endmodule
test/basic/header_import.v
0 → 100644
View file @
9c160c3d
module
top
;
localparam
P_FOO
=
10
;
initial
begin
$
display
(
P_FOO
)
;
end
endmodule
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