Commit 9acdb848 by Zachary Snow

ensure arrays used in nested ternary expressions are properly flattened

parent 95e1ed8d
...@@ -18,6 +18,7 @@ ...@@ -18,6 +18,7 @@
* Apply implicit port directions to tasks and functions * Apply implicit port directions to tasks and functions
* Support bare delay controls with real number delays * Support bare delay controls with real number delays
* Fix parsing of sized ports with implicit directions * Fix parsing of sized ports with implicit directions
* Ensure arrays used in nested ternary expressions are properly flattened
## v0.0.8 ## v0.0.8
......
...@@ -101,11 +101,6 @@ traverseLHSM :: LHS -> ST LHS ...@@ -101,11 +101,6 @@ traverseLHSM :: LHS -> ST LHS
traverseLHSM x = flatUsageM x >> return x traverseLHSM x = flatUsageM x >> return x
traverseAsgnM :: (LHS, Expr) -> ST (LHS, Expr) traverseAsgnM :: (LHS, Expr) -> ST (LHS, Expr)
traverseAsgnM (x, Mux cond y z) = do
flatUsageM x
flatUsageM y
flatUsageM z
return (x, Mux cond y z)
traverseAsgnM (x, y) = do traverseAsgnM (x, y) = do
flatUsageM x flatUsageM x
flatUsageM y flatUsageM y
...@@ -113,6 +108,8 @@ traverseAsgnM (x, y) = do ...@@ -113,6 +108,8 @@ traverseAsgnM (x, y) = do
class ScopeKey t => Key t where class ScopeKey t => Key t where
unbit :: t -> (t, Int) unbit :: t -> (t, Int)
split :: t -> Maybe (t, t)
split = const Nothing
instance Key Expr where instance Key Expr where
unbit (Bit e _) = (e', n + 1) unbit (Bit e _) = (e', n + 1)
...@@ -120,6 +117,8 @@ instance Key Expr where ...@@ -120,6 +117,8 @@ instance Key Expr where
unbit (Range e _ _) = (e', n) unbit (Range e _ _) = (e', n)
where (e', n) = unbit e where (e', n) = unbit e
unbit e = (e, 0) unbit e = (e, 0)
split (Mux _ a b) = Just (a, b)
split _ = Nothing
instance Key LHS where instance Key LHS where
unbit (LHSBit e _) = (e', n + 1) unbit (LHSBit e _) = (e', n + 1)
...@@ -132,6 +131,8 @@ instance Key Identifier where ...@@ -132,6 +131,8 @@ instance Key Identifier where
unbit x = (x, 0) unbit x = (x, 0)
flatUsageM :: Key k => k -> ST () flatUsageM :: Key k => k -> ST ()
flatUsageM k | Just (a, b) <- split k =
flatUsageM a >> flatUsageM b
flatUsageM k = do flatUsageM k = do
let (k', depth) = unbit k let (k', depth) = unbit k
details <- lookupElemM k' details <- lookupElemM k'
......
module mod(input [1:0] x [3]);
initial #1 $display("%b %b %b", x[0], x[1], x[2]);
endmodule
module top; module top;
logic [1:0] a [3]; logic [1:0] a [3];
logic [1:0] b [3]; logic [1:0] b [3];
...@@ -7,8 +11,20 @@ module top; ...@@ -7,8 +11,20 @@ module top;
logic [1:0] c [3]; logic [1:0] c [3];
logic [1:0] d [3]; logic [1:0] d [3];
logic [1:0] e [3]; logic [1:0] e [3];
logic [1:0] f [3];
initial x = 0; initial x = 0;
assign c = x ? d : e; assign c = x ? d : !x ? e : f;
logic [1:0] l [3];
logic [1:0] m [3];
logic [1:0] n [3];
initial begin
x = 1;
{l[0], l[1], l[2]} = { 2'bXZ, 2'b01, 2'b10 };
{m[0], m[1], m[2]} = { 2'b01, 2'b10, 2'b11 };
{n[0], n[1], n[2]} = { 2'b10, 2'b00, 2'b10 };
end
mod mod(!x ? l : x ? m : n);
generate generate
begin : A begin : A
...@@ -16,6 +32,6 @@ module top; ...@@ -16,6 +32,6 @@ module top;
logic [1:0] d [3]; logic [1:0] d [3];
end end
endgenerate endgenerate
assign A.d = 0; assign A.d = '{ default: 0 };
initial $display("%b %b", A.c[0], A.d[0]); initial $display("%b %b", A.c[0], A.d[0]);
endmodule endmodule
module mod(input [5:0] x);
initial #1 $display("%b %b %b", x[4+:2], x[2+:2], x[0+:2]);
endmodule
module top; module top;
reg [5:0] a; reg [5:0] a;
wire [5:0] b; wire [5:0] b;
...@@ -7,8 +11,20 @@ module top; ...@@ -7,8 +11,20 @@ module top;
wire [5:0] c; wire [5:0] c;
wire [5:0] d; wire [5:0] d;
wire [5:0] e; wire [5:0] e;
wire [5:0] f;
initial x = 0; initial x = 0;
assign c = x ? d : e; assign c = x ? d : !x ? e : f;
reg [5:0] l;
reg [5:0] m;
reg [5:0] n;
initial begin
x = 1;
l = { 2'bXZ, 2'b01, 2'b10 };
m = { 2'b01, 2'b10, 2'b11 };
n = { 2'b10, 2'b00, 2'b10 };
end
mod mod(!x ? l : x ? m : n);
generate generate
if (1) begin : A if (1) begin : A
......
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