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lvzhengyang
sv2v
Commits
9524f002
Commit
9524f002
authored
Oct 03, 2019
by
Zachary Snow
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support identifier delay values
parent
77dd1011
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2 changed files
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17 additions
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14 deletions
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-14
src/Language/SystemVerilog/Parser/Parse.y
+2
-1
test/basic/union.sv
+15
-13
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src/Language/SystemVerilog/Parser/Parse.y
View file @
9524f002
...
...
@@ -1017,9 +1017,10 @@ Sense :: { Sense }
DelayValue :: { Expr }
: Number { Number $1 }
| Identifier { Ident $1 }
| Identifier "::" Identifier { PSIdent $1 $3 }
-- TODO: Support these other DelayValues?
-- | real_number
-- | ps_identifier
-- | time_literal
-- | 1step
...
...
test/basic/union.sv
View file @
9524f002
...
...
@@ -32,29 +32,31 @@ module wrap;
C
c
;
D
d
;
localparam
delay
=
10
;
initial
begin
$
monitor
($
time
,
" %b %b"
,
a
.
x
,
a
.
y
)
;
a
.
x
=
5'b01101
;
#
10
;
a
.
y
=
5'b11101
;
#
10
;
a
.
x
=
5'b01101
;
#
delay
;
a
.
y
=
5'b11101
;
#
delay
;
$
monitor
($
time
,
" %b %b"
,
b
.
x
,
b
.
y
)
;
b
.
x
=
5'b01101
;
#
10
;
b
.
y
=
5'b11101
;
#
10
;
b
.
x
=
5'b01101
;
#
delay
;
b
.
y
=
5'b11101
;
#
delay
;
$
monitor
($
time
,
" %b %b"
,
c
.
x
,
c
.
y
)
;
c
.
x
=
5'b01101
;
#
10
;
c
.
y
=
5'b11101
;
#
10
;
c
.
x
=
5'b01101
;
#
delay
;
c
.
y
=
5'b11101
;
#
delay
;
$
monitor
($
time
,
" %b %b {%b %b} %b {%b %b}"
,
d
.
x
,
d
.
y
,
d
.
y
.
a
,
d
.
y
.
b
,
d
.
z
,
d
.
z
.
a
,
d
.
z
.
b
)
;
d
.
x
=
5'b01101
;
#
10
;
d
.
y
=
'
{
a
:
3'b110
,
b
:
2'b01
};
#
10
;
d
.
z
=
'
{
b
:
3'b110
,
a
:
2'b01
};
#
10
;
d
.
y
.
a
=
3'b010
;
#
10
;
d
.
y
.
b
=
2'b10
;
#
10
;
d
.
z
.
a
=
2'b11
;
#
10
;
d
.
z
.
b
=
3'b101
;
#
10
;
d
.
x
=
5'b01101
;
#
delay
;
d
.
y
=
'
{
a
:
3'b110
,
b
:
2'b01
};
#
delay
;
d
.
z
=
'
{
b
:
3'b110
,
a
:
2'b01
};
#
delay
;
d
.
y
.
a
=
3'b010
;
#
delay
;
d
.
y
.
b
=
2'b10
;
#
delay
;
d
.
z
.
a
=
2'b11
;
#
delay
;
d
.
z
.
b
=
3'b101
;
#
delay
;
end
...
...
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