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sv2v
Commit 95208947 by Zachary Snow
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unbased unsized conversion refactor 

- support ubased unsized bound to ports using injected constants
- explicit context-aware literal sizing for complex expressions
- fix infinite loop case in NestPI conversion
- elaborate size-casts of converted literals
parent 1903bc19
Showing with 140 additions and 4 deletions
src/Convert/NestPI.hs
......@@ -68,7 +68,7 @@ addItems pis existingPIs (item : items) =
, collectTypesM $ collectNestedTypesM collectTypenamesM
, collectExprsM $ collectNestedExprsM collectIdentsM
]
neededPIs = Set.difference usedPIs existingPIs
neededPIs = Set.difference (Set.difference usedPIs existingPIs) thisPI
itemsToAdd = map MIPackageItem $ Map.elems $
Map.restrictKeys pis neededPIs
addItems _ _ [] = []
......
src/Convert/SizeCast.hs
{-# LANGUAGE PatternSynonyms #-}
{- sv2v
- Author: Zachary Snow <zach@zachjs.com>
-
......@@ -54,6 +55,9 @@ traverseModuleItemM item = traverseExprsM traverseExprM item
traverseStmtM :: Stmt -> ST Stmt
traverseStmtM stmt = traverseStmtExprsM traverseExprM stmt
pattern ConvertedUU :: Char -> Expr
pattern ConvertedUU ch = Number ['1', '\'', 's', 'b', ch]
traverseExprM :: Expr -> ST Expr
traverseExprM =
traverseNestedExprsM convertExprM
......@@ -85,6 +89,13 @@ traverseExprM =
convertExprM other = return other
convertCastM :: Expr -> Expr -> ST Expr
convertCastM (s @ (Number str)) (e @ (ConvertedUU ch)) = do
typeMap <- get
case (exprSigning typeMap e, readNumber str) of
(Just Unspecified, Just n) -> return $ Number $
show n ++ "'b" ++ take (fromIntegral n) (repeat ch)
(Just sg, _) -> convertCastWithSigningM s e sg
_ -> return $ Cast (Right s) e
convertCastM s e = do
typeMap <- get
case exprSigning typeMap e of
......
test/basic/unbased_unsized.sv
`define TEST(value) \
logic [63:0] val_``value = 'value; \
initial $display(`"'value -> %b (%0d) %b (%0d)", \
initial $display(`"'value -> %b (%0d) %b (%0d)`", \
val_``value, $bits(val_``value), \
'value, $bits('value) \
);
......@@ -46,4 +46,69 @@ module top;
$display($bits(type('1)));
$display($bits(type(flag ? '1 : 'x)));
end
parameter P = 1;
M m1('0, '1, 'x, 'z);
M #( 2) m2('0, '1, 'x, 'z);
M #(28) m3('0, '1, 'x, 'z);
M #(29) m4('0, '1, 'x, 'z);
M #(30) m5('0, '1, 'x, 'z);
M #(31) m6('0, '1, 'x, 'z);
M #(32) m7('0, '1, 'x, 'z);
M #(33) m8('0, '1, 'x, 'z);
M #(34) m9('0, '1, 'x, 'z);
M #(31) mA(P ? '0 : '1, !P ? '0 : '1, 'x, 'z);
M #(34) mB(P ? '0 : '1, !P ? '0 : '1, 'x, 'z);
M #(31) mC(P ? '0 : '0 + '1, !P ? '0 : '0 + '1, 'x, 'z);
M #(34) mD(P ? '0 : '0 + '1, !P ? '0 : '0 + '1, 'x, 'z);
`define TEST_OP(left, op, right, expected) \
$display(`"%s: (left) op (right) -> %b (ref: %b)`", \
((left) op (right)) == expected ? "PASS" : "FAIL", \
(left) op (right), expected \
);
initial begin
`TEST_OP( 1'h1 , ==, '1, 1'b1)
`TEST_OP( 2'h3 , ==, '1, 1'b1)
`TEST_OP(31'h7fffffff , ==, '1, 1'b1)
`TEST_OP(32'hffffffff , ==, '1, 1'b1)
`TEST_OP(33'h1ffffffff, ==, '1, 1'b1)
`TEST_OP( 1'h1 , <=, '1, 1'b1)
`TEST_OP( 2'h3 , <=, '1, 1'b1)
`TEST_OP(31'h7fffffff , <=, '1, 1'b1)
`TEST_OP(32'hffffffff , <=, '1, 1'b1)
`TEST_OP(33'h1ffffffff, <=, '1, 1'b1)
`TEST_OP( 1'h1 , >=, '1, 1'b1)
`TEST_OP( 2'h3 , >=, '1, 1'b1)
`TEST_OP(31'h7fffffff , >=, '1, 1'b1)
`TEST_OP(32'hffffffff , >=, '1, 1'b1)
`TEST_OP(33'h1ffffffff, >=, '1, 1'b1)
`TEST_OP( 1'h1 , &, '1, 1'h1 )
`TEST_OP( 2'h3 , &, '1, 2'h3 )
`TEST_OP(31'h7fffffff , &, '1, 31'h7fffffff )
`TEST_OP(32'hffffffff , &, '1, 32'hffffffff )
`TEST_OP(33'h1ffffffff, &, '1, 33'h1ffffffff)
`TEST_OP(33'h1ffffffff, &, P ? '1 : '0, 33'h1ffffffff)
`TEST_OP(33'h1ffffffff, &, '1 & '1, 33'h1ffffffff)
`TEST_OP(33'h1ffffffff, &, !P ? '1 : '0 - 1, 33'h1ffffffff)
`TEST_OP(34'h3ffffffff, &, '0 - 1, 34'h3ffffffff)
`TEST_OP(1, ==, 2'h3 == '1, 1'b1)
end
endmodule
module M(a, b, c, d);
parameter W = 1;
input logic [W+0:1] a;
input logic [W+1:1] b;
input logic [W+2:1] c;
input logic [W+3:1] d;
initial $display("M W=%0d %b %b %b %b", W, a, b, c, d);
endmodule
test/basic/unbased_unsized.v
`define TEST(value) \
wire [63:0] val_``value = {64{1'b``value}}; \
initial $display(`"'value -> %b (%0d) %b (%0d)", \
initial $display(`"'value -> %b (%0d) %b (%0d)`", \
val_``value, $bits(val_``value), \
1'b``value, $bits(1'b``value) \
);
......@@ -25,7 +25,7 @@ module top;
flag = 1;
a = (flag ? 32'hFFFFFFFF : i);
b = (flag ? 32'hXXXXXXXX : i);
c = (flag ? 32'hFFFFFFFF: i);
c = (flag ? 32'hFFFFFFFF : i);
d = (flag ? 64'hFFFFFFFFFFFFFFFF : j);
e = (flag ? 64'hXXXXXXXXXXXXXXXX : j);
$display("%b", a);
......@@ -46,4 +46,64 @@ module top;
$display(1);
$display(1);
end
M m1({ 1 {1'b0}}, { 2 {1'b1}}, { 3 {1'bx}}, { 4 {1'bz}});
M #( 2) m2({ 2 {1'b0}}, { 3 {1'b1}}, { 4 {1'bx}}, { 5 {1'bz}});
M #(28) m3({28 {1'b0}}, {29 {1'b1}}, {30 {1'bx}}, {31 {1'bz}});
M #(29) m4({29 {1'b0}}, {30 {1'b1}}, {31 {1'bx}}, {32 {1'bz}});
M #(30) m5({30 {1'b0}}, {31 {1'b1}}, {32 {1'bx}}, {33 {1'bz}});
M #(31) m6({31 {1'b0}}, {32 {1'b1}}, {33 {1'bx}}, {34 {1'bz}});
M #(32) m7({32 {1'b0}}, {33 {1'b1}}, {34 {1'bx}}, {35 {1'bz}});
M #(33) m8({33 {1'b0}}, {34 {1'b1}}, {35 {1'bx}}, {36 {1'bz}});
M #(34) m9({34 {1'b0}}, {35 {1'b1}}, {36 {1'bx}}, {37 {1'bz}});
M #(31) mA({31 {1'b0}}, {32 {1'b1}}, {33 {1'bx}}, {34 {1'bz}});
M #(34) mB({34 {1'b0}}, {35 {1'b1}}, {36 {1'bx}}, {37 {1'bz}});
M #(31) mC({31 {1'b0}}, {32 {1'b1}}, {33 {1'bx}}, {34 {1'bz}});
M #(34) mD({34 {1'b0}}, {35 {1'b1}}, {36 {1'bx}}, {37 {1'bz}});
`define TEST_OP(left, op, right, expected) \
$display(`"PASS: (left) op (right) -> %b (ref: %b)`", expected, expected);
initial begin
`TEST_OP( 1'h1 , ==, '1, 1'b1)
`TEST_OP( 2'h3 , ==, '1, 1'b1)
`TEST_OP(31'h7fffffff , ==, '1, 1'b1)
`TEST_OP(32'hffffffff , ==, '1, 1'b1)
`TEST_OP(33'h1ffffffff, ==, '1, 1'b1)
`TEST_OP( 1'h1 , <=, '1, 1'b1)
`TEST_OP( 2'h3 , <=, '1, 1'b1)
`TEST_OP(31'h7fffffff , <=, '1, 1'b1)
`TEST_OP(32'hffffffff , <=, '1, 1'b1)
`TEST_OP(33'h1ffffffff, <=, '1, 1'b1)
`TEST_OP( 1'h1 , >=, '1, 1'b1)
`TEST_OP( 2'h3 , >=, '1, 1'b1)
`TEST_OP(31'h7fffffff , >=, '1, 1'b1)
`TEST_OP(32'hffffffff , >=, '1, 1'b1)
`TEST_OP(33'h1ffffffff, >=, '1, 1'b1)
`TEST_OP( 1'h1 , &, '1, 1'h1 )
`TEST_OP( 2'h3 , &, '1, 2'h3 )
`TEST_OP(31'h7fffffff , &, '1, 31'h7fffffff )
`TEST_OP(32'hffffffff , &, '1, 32'hffffffff )
`TEST_OP(33'h1ffffffff, &, '1, 33'h1ffffffff)
`TEST_OP(33'h1ffffffff, &, P ? '1 : '0, 33'h1ffffffff)
`TEST_OP(33'h1ffffffff, &, '1 & '1, 33'h1ffffffff)
`TEST_OP(33'h1ffffffff, &, !P ? '1 : '0 - 1, 33'h1ffffffff)
`TEST_OP(34'h3ffffffff, &, '0 - 1, 34'h3ffffffff)
`TEST_OP(1, ==, 2'h3 == '1, 1'b1)
end
endmodule
module M(a, b, c, d);
parameter W = 1;
input wire [W+0:1] a;
input wire [W+1:1] b;
input wire [W+2:1] c;
input wire [W+3:1] d;
initial $display("M W=%0d %b %b %b %b", W, a, b, c, d);
endmodule
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