Commit 945923b3 by Zachary Snow

cleaned up command line args module a bit

parent 7bc81ef6
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
module Convert (convert) where module Convert (convert) where
import Language.SystemVerilog.AST import Language.SystemVerilog.AST
import qualified Args as Args import Job (Target(..))
import qualified Convert.AlwaysKW import qualified Convert.AlwaysKW
import qualified Convert.CaseKW import qualified Convert.CaseKW
...@@ -19,24 +19,24 @@ import qualified Convert.StarPort ...@@ -19,24 +19,24 @@ import qualified Convert.StarPort
type Phase = AST -> AST type Phase = AST -> AST
phases :: Args.Target -> [Phase] phases :: Target -> [Phase]
phases Args.YOSYS = phases YOSYS =
[ Convert.Typedef.convert [ Convert.Typedef.convert
, Convert.PackedArray.convert , Convert.PackedArray.convert
, Convert.StarPort.convert , Convert.StarPort.convert
] ]
phases Args.VTR = phases VTR =
(phases Args.YOSYS) ++ (phases YOSYS) ++
[ Convert.AlwaysKW.convert [ Convert.AlwaysKW.convert
, Convert.CaseKW.convert , Convert.CaseKW.convert
, Convert.Logic.convert , Convert.Logic.convert
, Convert.SplitPortDecl.convert , Convert.SplitPortDecl.convert
] ]
run :: Args.Target -> Phase run :: Target -> Phase
run target = foldr (.) id $ phases target run target = foldr (.) id $ phases target
convert :: Args.Target -> Phase convert :: Target -> Phase
convert target = convert' convert target = convert'
where where
convert' :: Phase convert' :: Phase
......
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
- Command line arguments. - Command line arguments.
-} -}
module Args where module Job where
import System.Console.CmdArgs import System.Console.CmdArgs
...@@ -28,5 +28,5 @@ defaultJob = Job ...@@ -28,5 +28,5 @@ defaultJob = Job
&= details [ "sv2v converts SystemVerilog to Verilog." &= details [ "sv2v converts SystemVerilog to Verilog."
, "More info: https://github.com/zachjs/sv2v" ] , "More info: https://github.com/zachjs/sv2v" ]
readArgs :: IO Job readJob :: IO Job
readArgs = cmdArgs defaultJob readJob = cmdArgs defaultJob
{-# LANGUAGE DeriveDataTypeable #-}
{- sv2v {- sv2v
- Author: Zachary Snow <zach@zachjs.com> - Author: Zachary Snow <zach@zachjs.com>
- -
...@@ -8,21 +7,19 @@ ...@@ -8,21 +7,19 @@
import System.IO import System.IO
import System.Exit import System.Exit
import Args (readArgs, target, file) import Job (readJob, file, target)
import Convert (convert) import Convert (convert)
import Language.SystemVerilog.Parser import Language.SystemVerilog.Parser
main :: IO () main :: IO ()
main = do main = do
args <- readArgs job <- readJob
let filePath = file args -- parse the input file
let filePath = file job
content <- readFile filePath content <- readFile filePath
let ast = parseFile [] filePath content let ast = parseFile [] filePath content
let res = Right (convert (target args) ast) -- convert the file
case res of let ast' = convert (target job) ast
Left _ -> do -- print the converted file out
--hPrint stderr err hPrint stdout ast'
exitFailure exitSuccess
Right str -> do
hPrint stdout str
exitSuccess
...@@ -48,7 +48,7 @@ executable sv2v ...@@ -48,7 +48,7 @@ executable sv2v
Convert.Typedef Convert.Typedef
Convert.Traverse Convert.Traverse
-- sv2v CLI modules -- sv2v CLI modules
Args Job
ghc-options: ghc-options:
-O3 -O3
-threaded -threaded
......
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