allow parens around senses

910282fb · Zachary Snow · d2976170 · 910282fb
Commit 910282fb authored Oct 09, 2019 by Zachary Snow
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src/Language/SystemVerilog/Parser/Parse.y
+6 -3

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--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -1015,9 +1015,12 @@ Senses :: { Sense }
  | Senses "or" Sense { SenseOr $1 $3 }
  | Senses ","  Sense { SenseOr $1 $3 }
 Sense :: { Sense }
-  :           LHS { Sense        $1 }
-  | "posedge" LHS { SensePosedge $2 }
-  | "negedge" LHS { SenseNegedge $2 }
+  : "(" Sense ")"         {              $2 }
+  |               LHS     { Sense        $1 }
+  | "posedge"     LHS     { SensePosedge $2 }
+  | "negedge"     LHS     { SenseNegedge $2 }
+  | "posedge" "(" LHS ")" { SensePosedge $3 }
+  | "negedge" "(" LHS ")" { SenseNegedge $3 }

 DelayValue :: { Expr }
  : Number { Number $1 }