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lvzhengyang
sv2v
Commits
8cc649a0
Commit
8cc649a0
authored
Jan 05, 2020
by
Zachary Snow
Browse files
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Browse Files
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Plain Diff
made tests in basic suite yosys-friendly
- multipack - multipack_port - package_order - struct_array
parent
2266dd69
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Showing
7 changed files
with
68 additions
and
107 deletions
+68
-107
test/basic/multipack.sv
+26
-44
test/basic/multipack.v
+34
-53
test/basic/multipack_port.sv
+2
-3
test/basic/multipack_port.v
+2
-3
test/basic/package_order.sv
+1
-1
test/basic/package_order.v
+1
-1
test/basic/struct_array.v
+2
-2
No files found.
test/basic/multipack.sv
View file @
8cc649a0
`define
PRINT
(
arr
,
a
,
b
)
\
$
display
(
arr
[
0
+
a
][
0
+
b
])
;
\
$
display
(
arr
[
0
+
a
][
1
+
b
])
;
\
$
display
(
arr
[
0
+
a
][
2
+
b
])
;
\
$
display
(
arr
[
1
+
a
][
0
+
b
])
;
\
$
display
(
arr
[
1
+
a
][
1
+
b
])
;
\
$
display
(
arr
[
1
+
a
][
2
+
b
])
;
\
$
display
(
arr
[
2
+
a
][
0
+
b
])
;
\
$
display
(
arr
[
2
+
a
][
1
+
b
])
;
\
$
display
(
arr
[
2
+
a
][
2
+
b
])
;
\
$
display
(
arr
[
3
+
a
][
0
+
b
])
;
\
$
display
(
arr
[
3
+
a
][
1
+
b
])
;
\
$
display
(
arr
[
3
+
a
][
2
+
b
])
;
\
$
display
(
arr
[
4
+
a
][
0
+
b
])
;
\
$
display
(
arr
[
4
+
a
][
1
+
b
])
;
\
$
display
(
arr
[
4
+
a
][
2
+
b
])
;
module
Example
;
module
Example
;
initial
$
monitor
(
"%b %b %b %b %b %b %b %b %b"
,
arr1
,
arr2
,
arr3
,
arr4
,
arr5
,
arr6
,
arr7
,
arr8
,
arr9
)
;
typedef
logic
[
2
:
0
]
Pack
;
typedef
logic
[
2
:
0
]
Pack
;
Pack
[
4
:
0
]
arr1
;
Pack
[
4
:
0
]
arr1
;
Pack
[
4
:
0
]
arr2
;
Pack
[
4
:
0
]
arr2
;
Pack
[
4
:
0
]
arr3
;
Pack
[
4
:
0
]
arr3
;
initial
begin
initial
begin
arr1
=
'b100101010100100
;
#
1
;
arr1
=
'b100101010100100
;
arr1
[
0
][
1
]
=
~
arr1
[
0
][
1
]
;
#
1
;
arr1
[
0
][
1
]
=
~
arr1
[
0
][
1
]
;
arr1
[
4
][
2
]
=
~
arr1
[
4
][
2
]
;
#
1
;
arr1
[
4
][
2
]
=
~
arr1
[
4
][
2
]
;
`PRINT
(
arr1
,
0
,
0
)
#
1
;
arr2
=
'b100101000110101
;
arr2
=
'b100101000110101
;
#
1
;
arr3
=
'b100100111101010
;
`PRINT
(
arr2
,
0
,
0
)
#
1
;
arr3
[
1
]
=
arr3
[
2
]
;
arr3
=
'b100100111101010
;
arr3
[
1
]
=
arr3
[
2
]
;
`PRINT
(
arr3
,
0
,
0
)
end
end
Pack
[
5
:
1
]
arr4
;
Pack
[
5
:
1
]
arr4
;
Pack
[
5
:
1
]
arr5
;
Pack
[
5
:
1
]
arr5
;
Pack
[
5
:
1
]
arr6
;
Pack
[
5
:
1
]
arr6
;
initial
begin
initial
begin
arr4
=
'b100101010100100
;
#
1
;
arr4
=
'b100101010100100
;
arr4
[
1
][
1
]
=
~
arr4
[
1
][
1
]
;
#
1
;
arr4
[
1
][
1
]
=
~
arr4
[
1
][
1
]
;
arr4
[
5
][
2
]
=
~
arr4
[
5
][
2
]
;
#
1
;
arr4
[
5
][
2
]
=
~
arr4
[
5
][
2
]
;
`PRINT
(
arr4
,
1
,
0
)
#
1
;
arr5
=
'b100101000110101
;
arr5
=
'b100101000110101
;
#
1
;
arr6
=
'b100100111101010
;
`PRINT
(
arr5
,
1
,
0
)
#
1
;
arr6
[
2
]
=
arr6
[
3
]
;
arr6
=
'b100100111101010
;
arr6
[
2
]
=
arr6
[
3
]
;
`PRINT
(
arr6
,
1
,
0
)
end
end
Pack
[
1
:
5
]
arr7
;
Pack
[
1
:
5
]
arr7
;
Pack
[
1
:
5
]
arr8
;
Pack
[
1
:
5
]
arr8
;
Pack
[
1
:
5
]
arr9
;
Pack
[
1
:
5
]
arr9
;
initial
begin
initial
begin
arr7
=
'b100101010100100
;
#
1
;
arr7
=
'b100101010100100
;
arr7
[
1
][
1
]
=
~
arr7
[
1
][
1
]
;
#
1
;
arr7
[
1
][
1
]
=
~
arr7
[
1
][
1
]
;
arr7
[
5
][
2
]
=
~
arr7
[
5
][
2
]
;
#
1
;
arr7
[
5
][
2
]
=
~
arr7
[
5
][
2
]
;
`PRINT
(
arr7
,
1
,
0
)
#
1
;
arr8
=
'b100101000110101
;
arr8
=
'b100101000110101
;
#
1
;
arr9
=
'b100100111101010
;
`PRINT
(
arr8
,
1
,
0
)
#
1
;
arr9
[
2
]
=
arr9
[
3
]
;
arr9
=
'b100100111101010
;
arr9
[
2
]
=
arr9
[
3
]
;
`PRINT
(
arr9
,
1
,
0
)
end
end
endmodule
endmodule
test/basic/multipack.v
View file @
8cc649a0
`define
PRINT
(
arr
,
a
,
b
)
\
$
display
(
arr
[
0
+
a
][
0
+
b
])
;
\
$
display
(
arr
[
0
+
a
][
1
+
b
])
;
\
$
display
(
arr
[
0
+
a
][
2
+
b
])
;
\
$
display
(
arr
[
1
+
a
][
0
+
b
])
;
\
$
display
(
arr
[
1
+
a
][
1
+
b
])
;
\
$
display
(
arr
[
1
+
a
][
2
+
b
])
;
\
$
display
(
arr
[
2
+
a
][
0
+
b
])
;
\
$
display
(
arr
[
2
+
a
][
1
+
b
])
;
\
$
display
(
arr
[
2
+
a
][
2
+
b
])
;
\
$
display
(
arr
[
3
+
a
][
0
+
b
])
;
\
$
display
(
arr
[
3
+
a
][
1
+
b
])
;
\
$
display
(
arr
[
3
+
a
][
2
+
b
])
;
\
$
display
(
arr
[
4
+
a
][
0
+
b
])
;
\
$
display
(
arr
[
4
+
a
][
1
+
b
])
;
\
$
display
(
arr
[
4
+
a
][
2
+
b
])
;
module
Example
;
module
Example
;
reg
[
4
:
0
][
2
:
0
]
arr1
;
initial
reg
[
4
:
0
][
2
:
0
]
arr2
;
$
monitor
(
"%b %b %b %b %b %b %b %b %b"
,
reg
[
4
:
0
][
2
:
0
]
arr3
;
arr1
,
arr2
,
arr3
,
arr4
,
arr5
,
arr6
,
arr7
,
arr8
,
arr9
)
;
reg
[
14
:
0
]
arr1
;
reg
[
14
:
0
]
arr2
;
reg
[
14
:
0
]
arr3
;
initial
begin
initial
begin
arr1
=
'b100101010100100
;
#
1
;
arr1
=
'b100101010100100
;
arr1
[
0
][
1
]
=
~
arr1
[
0
][
1
]
;
#
1
;
arr1
[
0
*
3
+
1
]
=
~
arr1
[
0
*
3
+
1
]
;
arr1
[
4
][
2
]
=
~
arr1
[
4
][
2
]
;
#
1
;
arr1
[
4
*
3
+
2
]
=
~
arr1
[
4
*
3
+
2
]
;
`PRINT
(
arr1
,
0
,
0
)
#
1
;
arr2
=
'b100101000110101
;
arr2
=
'b100101000110101
;
#
1
;
arr3
=
'b100100111101010
;
`PRINT
(
arr2
,
0
,
0
)
#
1
;
arr3
[
1
*
3
+:
3
]
=
arr3
[
2
*
3
+:
3
]
;
arr3
=
'b100100111101010
;
arr3
[
1
]
=
arr3
[
2
]
;
`PRINT
(
arr3
,
0
,
0
)
end
end
reg
[
5
:
1
][
2
:
0
]
arr4
;
reg
[
14
:
0
]
arr4
;
reg
[
5
:
1
][
2
:
0
]
arr5
;
reg
[
14
:
0
]
arr5
;
reg
[
5
:
1
][
2
:
0
]
arr6
;
reg
[
14
:
0
]
arr6
;
initial
begin
initial
begin
arr4
=
'b100101010100100
;
#
1
;
arr4
=
'b100101010100100
;
arr4
[
1
][
1
]
=
~
arr4
[
1
][
1
]
;
#
1
;
arr4
[
0
*
3
+
1
]
=
~
arr4
[
0
*
3
+
1
]
;
arr4
[
5
][
2
]
=
~
arr4
[
5
][
2
]
;
#
1
;
arr4
[
4
*
3
+
2
]
=
~
arr4
[
4
*
3
+
2
]
;
`PRINT
(
arr4
,
1
,
0
)
#
1
;
arr5
=
'b100101000110101
;
arr5
=
'b100101000110101
;
#
1
;
arr6
=
'b100100111101010
;
`PRINT
(
arr5
,
1
,
0
)
#
1
;
arr6
[
1
*
3
+:
3
]
=
arr6
[
2
*
3
+:
3
]
;
arr6
=
'b100100111101010
;
arr6
[
2
]
=
arr6
[
3
]
;
`PRINT
(
arr6
,
1
,
0
)
end
end
reg
[
1
:
5
][
2
:
0
]
arr7
;
reg
[
1
4
:
0
]
arr7
;
reg
[
1
:
5
][
2
:
0
]
arr8
;
reg
[
1
4
:
0
]
arr8
;
reg
[
1
:
5
][
2
:
0
]
arr9
;
reg
[
1
4
:
0
]
arr9
;
initial
begin
initial
begin
arr7
=
'b100101010100100
;
#
1
;
arr7
=
'b100101010100100
;
arr7
[
1
][
1
]
=
~
arr7
[
1
][
1
]
;
#
1
;
arr7
[(
4
-
0
)
*
3
+
1
]
=
~
arr7
[(
4
-
0
)
*
3
+
1
]
;
arr7
[
5
][
2
]
=
~
arr7
[
5
][
2
]
;
#
1
;
arr7
[(
4
-
4
)
*
3
+
2
]
=
~
arr7
[(
4
-
4
)
*
3
+
2
]
;
`PRINT
(
arr7
,
1
,
0
)
#
1
;
arr8
=
'b100101000110101
;
arr8
=
'b100101000110101
;
#
1
;
arr9
=
'b100100111101010
;
`PRINT
(
arr8
,
1
,
0
)
#
1
;
arr9
[(
4
-
1
)
*
3
+:
3
]
=
arr9
[(
4
-
2
)
*
3
+:
3
]
;
arr9
=
'b100100111101010
;
arr9
[
2
]
=
arr9
[
3
]
;
`PRINT
(
arr9
,
1
,
0
)
end
end
endmodule
endmodule
test/basic/multipack_port.sv
View file @
8cc649a0
...
@@ -22,12 +22,11 @@ module top;
...
@@ -22,12 +22,11 @@ module top;
initial
begin
initial
begin
clock
=
1
;
clock
=
1
;
forever
#
1
clock
=
~
clock
;
repeat
(
100
)
#
1
clock
=
~
clock
;
end
end
initial
begin
:
foo
initial
begin
:
foo
$
monitor
(
"%d %b%b%b%b%b"
,
$
time
,
data
[
0
]
,
data
[
1
]
,
data
[
2
]
,
data
[
3
]
,
data
[
4
])
;
$
monitor
(
"%d %b%b%b%b%b"
,
$
time
,
data
[
0
]
,
data
[
1
]
,
data
[
2
]
,
data
[
3
]
,
data
[
4
])
;
#
100
;
$
finish
()
;
end
end
endmodule
endmodule
test/basic/multipack_port.v
View file @
8cc649a0
...
@@ -22,12 +22,11 @@ module top;
...
@@ -22,12 +22,11 @@ module top;
initial
begin
initial
begin
clock
=
1
;
clock
=
1
;
forever
#
1
clock
=
~
clock
;
repeat
(
100
)
#
1
clock
=
~
clock
;
end
end
initial
begin
:
foo
initial
begin
:
foo
$
monitor
(
"%d %b"
,
$
time
,
data
)
;
$
monitor
(
"%d %b"
,
$
time
,
data
)
;
#
100
;
$
finish
()
;
end
end
endmodule
endmodule
test/basic/package_order.sv
View file @
8cc649a0
...
@@ -17,5 +17,5 @@ endmodule
...
@@ -17,5 +17,5 @@ endmodule
module
top
;
module
top
;
logic
[
evil_pkg
::
B
-
1
:
0
]
foo
;
logic
[
evil_pkg
::
B
-
1
:
0
]
foo
;
evil_mdl
x
(
foo
)
;
evil_mdl
x
(
foo
)
;
initial
$
display
(
foo
)
;
initial
$
monitor
(
foo
)
;
endmodule
endmodule
test/basic/package_order.v
View file @
8cc649a0
...
@@ -13,5 +13,5 @@ module top;
...
@@ -13,5 +13,5 @@ module top;
localparam
evil_pkg_B
=
evil_pkg_Z
;
localparam
evil_pkg_B
=
evil_pkg_Z
;
wire
[
evil_pkg_B
-
1
:
0
]
foo
;
wire
[
evil_pkg_B
-
1
:
0
]
foo
;
evil_mdl
x
(
foo
)
;
evil_mdl
x
(
foo
)
;
initial
$
display
(
foo
)
;
initial
$
monitor
(
foo
)
;
endmodule
endmodule
test/basic/struct_array.v
View file @
8cc649a0
module
Unpacker
(
in
,
select
,
a
,
b
,
c
)
;
module
Unpacker
(
in
,
select
,
a
,
b
,
c
)
;
parameter
WIDTH
=
8
;
parameter
WIDTH
=
8
;
input
wire
[
WIDTH
-
1
:
0
][
6
:
0
]
in
;
input
wire
[
WIDTH
*
7
-
1
:
0
]
in
;
input
wire
[$
clog2
(
WIDTH
)
-
1
:
0
]
select
;
input
wire
[$
clog2
(
WIDTH
)
-
1
:
0
]
select
;
output
wire
a
;
output
wire
a
;
output
wire
[
3
:
0
]
b
;
output
wire
[
3
:
0
]
b
;
output
wire
[
1
:
0
]
c
;
output
wire
[
1
:
0
]
c
;
wire
[
6
:
0
]
p
;
wire
[
6
:
0
]
p
;
assign
p
=
in
[
select
]
;
assign
p
=
in
[
select
*
7
+:
7
]
;
assign
a
=
p
[
6
:
6
]
;
assign
a
=
p
[
6
:
6
]
;
assign
b
=
p
[
5
:
2
]
;
assign
b
=
p
[
5
:
2
]
;
assign
c
=
p
[
1
:
0
]
;
assign
c
=
p
[
1
:
0
]
;
...
...
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