Basic build setup!

Data/BitVec.hs

@@ -8,7 +8,6 @@ module Data.BitVec
   ) where
 
 import Data.Bits
-import Data.Semigroup
 
 data BitVec = BitVec Int Integer deriving (Show, Eq)
 
@@ -18,13 +17,13 @@ instance Num BitVec where
   BitVec w1 v1 * BitVec w2 v2 = bitVec (max w1 w2) (v1 * v2)
   abs = id
   signum (BitVec _ v) = if v == 0 then bitVec 1 0 else bitVec 1 1
-  fromInteger i = bitVec (width i) i
+  fromInteger i = bitVec (wid i) i
     where
-    width :: Integer -> Int
-    width a
+    wid :: Integer -> Int
+    wid a
       | a ==  0   = 0
       | a == -1   = 1
-      | otherwise = 1 + width (shiftR a 1)
+      | otherwise = 1 + wid (shiftR a 1)
 
 instance Bits BitVec where
   BitVec w1 v1 .&.   BitVec w2 v2 = bitVec (max w1 w2) (v1 .&.   v2)

Language/SystemVerilog/Parser/.gitignore

+Lex.hs
+Parse.hs

Makefile

+.PHONY: all sv2v clean
+
+all: sv2v
+
+Language/SystemVerilog/Parser/Lex.hs: Language/SystemVerilog/Parser/Lex.x
+	alex -g Language/SystemVerilog/Parser/Lex.x -o Language/SystemVerilog/Parser/Lex.hs
+
+Language/SystemVerilog/Parser/Parse.hs: Language/SystemVerilog/Parser/Parse.y
+	happy -agc Language/SystemVerilog/Parser/Parse.y -o Language/SystemVerilog/Parser/Parse.hs
+
+sv2v: Language/SystemVerilog/Parser/Lex.hs Language/SystemVerilog/Parser/Parse.hs
+	cabal install
+
+clean:
+	rm -f Language/SystemVerilog/Parser/Lex.hs
+	rm -f Language/SystemVerilog/Parser/Parse.hs

sv2v.cabal

@@ -45,8 +45,11 @@ library
 executable sv2v
   default-language: Haskell2010
   main-is: sv2v.hs
-  Build-Depends:
+  build-depends:
+    array,
     base
+  other-modules:
+    Language.SystemVerilog.Parser
   ghc-options:
     -O3
     -threaded
@@ -58,4 +61,3 @@ executable sv2v
 source-repository head
   type:     git
   location: git://github.com/zachjs/sv2v.git
-

sv2v.hs

 {- sv2v
-   Author: Zachary Snow <zach@zachjs.com>
-
-   conversion entry point
--}
+ - Author: Zachary Snow <zach@zachjs.com>
+ -
+ - conversion entry point
+ -}
 
 import System.IO
 import System.Exit
+import System.Environment
+
+import Language.SystemVerilog.Parser
 
 main :: IO ()
 main = do
-    let res = Left "unimplemented"
+    [filePath] <- getArgs
+    content <- readFile filePath
+    let ast = parseFile [] filePath content
+    let res = Left ast
     case res of
         Left  err -> do
             hPrint stderr err