fixed handling of 3+ dimensional packed arrays

src/Convert/PackedArray.hs

@@ -116,7 +116,7 @@ flattenRanges rs =
         rY = endianCondRange r2 rYY rYN
         rN = endianCondRange r2 rNY rNN
         r = endianCondRange r1 rY rN
-        rs' = (tail $ tail rs) ++ [r]
+        rs' = r : (tail $ tail rs)
 
 flattenRangesHelp :: Range -> Range -> Range
 flattenRangesHelp (s1, e1) (s2, e2) =
@@ -185,6 +185,7 @@ rewriteModuleItem info =
                 x' = ':' : x
                 mode' = mode
                 size = rangeSize dimOuter
+                base = endianCondExpr dimOuter (snd dimOuter) (fst dimOuter)
                 range' =
                     case mode of
                         NonIndexed   ->
@@ -192,8 +193,8 @@ rewriteModuleItem info =
                             where
                                 lo = BinOp Mul size (snd range)
                                 hi = BinOp Sub (BinOp Add lo (BinOp Mul (rangeSize range) size)) (Number "1")
-                        IndexedPlus  -> (BinOp Mul size (fst range), BinOp Mul size (snd range))
-                        IndexedMinus -> (BinOp Mul size (fst range), BinOp Mul size (snd range))
+                        IndexedPlus  -> (BinOp Add (BinOp Mul size (fst range)) base, BinOp Mul size (snd range))
+                        IndexedMinus -> (BinOp Add (BinOp Mul size (fst range)) base, BinOp Mul size (snd range))
         ---- TODO: I'm not sure how these should be handled yet.
         ----rewriteExpr (orig @ (Range (Bit (Ident x) idxInner) modeOuter rangeOuter)) =
         ----    if Map.member x typeDims

test/basic/flatten_three.sv

+`define CASE(name, dims, a, b, c) \
+module name(clock, in, out); \
+    input wire clock, in; \
+    output logic dims out; \
+    initial out[0+a] = 0; \
+    initial out[1+a] = 0; \
+    initial out[2+a] = 0; \
+    always @(posedge clock) begin \
+ \
+        out[2+a][4+b][1+c] = out[2+a][4+b][0+c]; \
+        out[2+a][4+b][0+c] = out[2+a][3+b][1+c]; \
+        out[2+a][3+b][1+c] = out[2+a][3+b][0+c]; \
+        out[2+a][3+b][0+c] = out[2+a][2+b][1+c]; \
+        out[2+a][2+b][1+c] = out[2+a][2+b][0+c]; \
+        out[2+a][2+b][0+c] = out[2+a][1+b][1+c]; \
+        out[2+a][1+b][1+c] = out[2+a][1+b][0+c]; \
+        out[2+a][1+b][0+c] = out[2+a][0+b][1+c]; \
+        out[2+a][0+b][1+c] = out[2+a][0+b][0+c]; \
+        out[2+a][0+b][0+c] = out[1+a][4+b][1+c]; \
+ \
+        out[1+a][4+b][1+c] = out[1+a][4+b][0+c]; \
+        out[1+a][4+b][0+c] = out[1+a][3+b][1+c]; \
+        out[1+a][3+b][1+c] = out[1+a][3+b][0+c]; \
+        out[1+a][3+b][0+c] = out[1+a][2+b][1+c]; \
+        out[1+a][2+b][1+c] = out[1+a][2+b][0+c]; \
+        out[1+a][2+b][0+c] = out[1+a][1+b][1+c]; \
+        out[1+a][1+b][1+c] = out[1+a][1+b][0+c]; \
+        out[1+a][1+b][0+c] = out[1+a][0+b][1+c]; \
+        out[1+a][0+b][1+c] = out[1+a][0+b][0+c]; \
+        out[1+a][0+b][0+c] = out[0+a][4+b][1+c]; \
+ \
+        out[0+a][4+b][1+c] = out[0+a][4+b][0+c]; \
+        out[0+a][4+b][0+c] = out[0+a][3+b][1+c]; \
+        out[0+a][3+b][1+c] = out[0+a][3+b][0+c]; \
+        out[0+a][3+b][0+c] = out[0+a][2+b][1+c]; \
+        out[0+a][2+b][1+c] = out[0+a][2+b][0+c]; \
+        out[0+a][2+b][0+c] = out[0+a][1+b][1+c]; \
+        out[0+a][1+b][1+c] = out[0+a][1+b][0+c]; \
+        out[0+a][1+b][0+c] = out[0+a][0+b][1+c]; \
+        out[0+a][0+b][1+c] = out[0+a][0+b][0+c]; \
+        out[0+a][0+b][0+c] = in; \
+ \
+    end \
+endmodule
+
+`CASE(A1, [2:0][4:0][1:0], 0, 0, 0)
+`CASE(A2, [0:2][0:4][1:0], 0, 0, 0)
+`CASE(A3, [0:2][4:0][1:0], 0, 0, 0)
+`CASE(A4, [2:0][0:4][1:0], 0, 0, 0)
+
+`CASE(B1, [3:1][5:1][1:0], 1, 1, 0)
+`CASE(B2, [1:3][1:5][1:0], 1, 1, 0)
+`CASE(B3, [1:3][5:1][1:0], 1, 1, 0)
+`CASE(B4, [3:1][1:5][1:0], 1, 1, 0)
+
+`CASE(C1, [4:2][6:2][1:0], 2, 2, 0)
+`CASE(C2, [2:4][2:6][1:0], 2, 2, 0)
+`CASE(C3, [2:4][6:2][1:0], 2, 2, 0)
+`CASE(C4, [4:2][2:6][1:0], 2, 2, 0)
+
+`CASE(D1, [5:3][6:2][1:0], 3, 2, 0)
+`CASE(D2, [3:5][2:6][1:0], 3, 2, 0)
+`CASE(D3, [3:5][6:2][1:0], 3, 2, 0)
+`CASE(D4, [5:3][2:6][1:0], 3, 2, 0)
+
+`CASE(E1, [2:0][4:0][0:1], 0, 0, 0)
+`CASE(E2, [0:2][0:4][0:1], 0, 0, 0)
+`CASE(E3, [0:2][4:0][0:1], 0, 0, 0)
+`CASE(E4, [2:0][0:4][0:1], 0, 0, 0)
+
+`CASE(F1, [5:3][6:2][1:0], 3, 2, 0)
+`CASE(F2, [3:5][2:6][1:0], 3, 2, 0)
+`CASE(F3, [3:5][6:2][1:0], 3, 2, 0)
+`CASE(F4, [5:3][2:6][1:0], 3, 2, 0)
+
+`CASE(G1, [5:3][6:2][2:1], 3, 2, 1)
+`CASE(G2, [3:5][2:6][2:1], 3, 2, 1)
+`CASE(G3, [3:5][6:2][2:1], 3, 2, 1)
+`CASE(G4, [5:3][2:6][2:1], 3, 2, 1)
+
+`CASE(H1, [5:3][6:2][1:2], 3, 2, 1)
+`CASE(H2, [3:5][2:6][1:2], 3, 2, 1)
+`CASE(H3, [3:5][6:2][1:2], 3, 2, 1)
+`CASE(H4, [5:3][2:6][1:2], 3, 2, 1)

test/basic/flatten_three.v

+// iverilog supports multi-dimensional packed arrays
+`include "flatten_three.sv"

test/basic/flatten_three_tb.v

+`define FOO(tag) \
+    wire [29:0] tag``one_out, tag``two_out, tag``thr_out, tag``fou_out; \
+    tag``1 tag``one(.clock(clock), .in(in), .out(tag``one_out)); \
+    tag``2 tag``two(.clock(clock), .in(in), .out(tag``two_out)); \
+    tag``3 tag``thr(.clock(clock), .in(in), .out(tag``thr_out)); \
+    tag``4 tag``fou(.clock(clock), .in(in), .out(tag``fou_out)); \
+    integer tag``i; \
+    initial begin \
+        for (tag``i = 0; tag``i < 40; tag``i++) begin \
+            #2; \
+            $display(`"tag", $time, ": %h %30b %30b %30b %30b", in, \
+                tag``one_out, tag``two_out, tag``thr_out, tag``fou_out); \
+        end \
+    end
+
+module top;
+    reg clock, in;
+
+    initial begin
+        clock = 1;
+        forever #1 clock = ~clock;
+    end
+
+    integer i;
+    localparam [40:0] pattern = 40'hfadf014932;
+    initial begin
+        for (i = 0; i < 40; i++) begin
+            in = pattern[i];
+            #2;
+        end
+        $finish;
+    end
+
+    `FOO(A)
+    `FOO(B)
+    `FOO(C)
+    `FOO(D)
+    `FOO(E)
+    `FOO(F)
+    `FOO(G)
+    `FOO(H)
+
+endmodule