support for ++ and -- as bare Stmts

848f8cbd · Zachary Snow · 69a5585a · 848f8cbd
Commit 848f8cbd authored Mar 28, 2019 by Zachary Snow
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src/Language/SystemVerilog/Parser/Parse.y
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--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -543,6 +543,8 @@ Stmt :: { Stmt }
  | LHS AsgnOp Expr ";" { AsgnBlk $2 $1 $3 }
  | Identifier      ";" { Subroutine $1 [] }
  | LHS "<=" opt(DelayOrEventControl) Expr ";" { Asgn $3 $1 $4 }
+  | LHS IncOrDecOperator ";" { AsgnBlk (AsgnOp $2) $1 (Number "1") }
+  | IncOrDecOperator LHS ";" { AsgnBlk (AsgnOp $1) $2 (Number "1") }
 StmtNonAsgn :: { Stmt }
  : ";" { Null }
  | "begin" opt(Tag) DeclsAndStmts "end" opt(Tag) { Block (combineTags $2 $5) (fst $3) (snd $3) }