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lvzhengyang
sv2v
Commits
80154feb
Commit
80154feb
authored
Jun 25, 2020
by
Zachary Snow
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logic conversion notices procedural assignments in tasks and functions
parent
24071d74
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src/Convert/Logic.hs
+2
-0
test/basic/logic_tf.sv
+16
-0
test/basic/logic_tf.v
+20
-0
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src/Convert/Logic.hs
View file @
80154feb
...
@@ -171,6 +171,8 @@ regIdents :: ModuleItem -> Writer Idents ()
...
@@ -171,6 +171,8 @@ regIdents :: ModuleItem -> Writer Idents ()
regIdents
(
item
@
AlwaysC
{})
=
regIdents'
item
regIdents
(
item
@
AlwaysC
{})
=
regIdents'
item
regIdents
(
item
@
Initial
{})
=
regIdents'
item
regIdents
(
item
@
Initial
{})
=
regIdents'
item
regIdents
(
item
@
Final
{})
=
regIdents'
item
regIdents
(
item
@
Final
{})
=
regIdents'
item
regIdents
(
item
@
(
MIPackageItem
Task
{}))
=
regIdents'
item
regIdents
(
item
@
(
MIPackageItem
Function
{}))
=
regIdents'
item
regIdents
_
=
return
()
regIdents
_
=
return
()
regIdents'
::
ModuleItem
->
Writer
Idents
()
regIdents'
::
ModuleItem
->
Writer
Idents
()
...
...
test/basic/logic_tf.sv
0 → 100644
View file @
80154feb
module
top
;
logic
x
,
y
,
z
;
task
t
;
x
=
1
;
endtask
function
f
;
y
=
1
;
f
=
0
;
endfunction
assign
z
=
0
;
initial
begin
t
;
$
display
(
"%b %b %b %b"
,
x
,
y
,
z
,
f
())
;
$
display
(
"%b %b %b %b"
,
x
,
y
,
z
,
f
())
;
end
endmodule
test/basic/logic_tf.v
0 → 100644
View file @
80154feb
module
top
;
reg
x
,
y
;
wire
z
;
task
t
;
x
=
1
;
endtask
function
f
;
input
x
;
begin
y
=
1
;
f
=
0
;
end
endfunction
assign
z
=
0
;
initial
begin
t
;
$
display
(
"%b %b %b %b"
,
x
,
y
,
z
,
f
(
0
))
;
$
display
(
"%b %b %b %b"
,
x
,
y
,
z
,
f
(
0
))
;
end
endmodule
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