added Reid's new tests

test/relong/gen_struct.sv

+`default_nettype none
+
+typedef struct packed {
+    logic [1:0] last;
+    logic [3:0] middle;
+    logic [1:0] first;
+} MyStruct_t;
+
+
+module Example(
+    input logic [3:0] a,
+    output logic [31:0] all
+);
+
+    generate
+        genvar i;
+        for(i = 0; i < 4; i = i + 1) begin
+            MyStruct_t s;
+            always_comb begin
+                s = '{
+                    first: i,
+                    middle: a,
+                    last: 3 - i
+                };
+            end
+            assign all[i*$bits(s)+:$bits(s)] = s;
+        end
+    endgenerate
+
+endmodule
\ No newline at end of file

test/relong/gen_struct.v

+`default_nettype none
+
+module Example(
+    input wire [3:0] a,
+    output wire [31:0] all
+);
+
+    function [1:0] __truncate_to_2_bits(input [1:0] i);
+        __truncate_to_2_bits = i;
+    endfunction
+
+    generate
+        genvar i;
+        for(i = 0; i < 4; i = i + 1) begin : __gen_loop
+            reg [7:0] s;
+            always @* begin
+                s = {__truncate_to_2_bits(3-i), a, __truncate_to_2_bits(i)};
+                // s = '{
+                //     first: i,
+                //     middle: a,
+                //     last: 3 - i
+                // };
+            end
+            assign all[i*8+:8] = s;
+        end
+    endgenerate
+
+endmodule
\ No newline at end of file

test/relong/gen_struct_tb.v

+`default_nettype none
+
+module top;
+
+    wire [3:0] a;
+    wire [31:0] result;
+
+    Example dut(
+        .a(a),
+        .all(result)
+    );
+
+    reg [4:0] _a;
+    assign a = _a[3:0];
+    initial begin
+        $monitor($time, "a: %b result: %h", a, result);
+        for (_a = 0; _a < 5'hf; _a = _a + 1) begin
+            #10;
+        end
+        $finish;
+    end
+
+
+endmodule
\ No newline at end of file

test/relong/module_struct.sv

+`default_nettype none
+
+typedef struct packed {
+    logic [1:0] last;
+    logic [1:0] first;
+} MyStruct_t;
+
+
+module Example(
+    input logic [1:0] a, b,
+    output logic [3:0] result
+);
+
+   MyStruct_t s;
+   assign result = s;
+
+  SubModule sub(
+    .in(a),
+    .out(s.last)
+  );
+
+   always_comb begin
+        s.first = b;
+   end
+
+endmodule
+
+module SubModule(
+  input logic [1:0] in,
+  output logic [1:0] out
+);
+
+  assign out = in;
+
+endmodule
\ No newline at end of file

test/relong/module_struct.v

+`default_nettype none
+
+// typedef struct packed {
+//     logic [1:0] last;
+//     logic [1:0] first;
+// } MyStruct_t;
+
+
+module Example(
+    input wire [1:0] a, b,
+    output wire [3:0] result
+);
+
+   reg [3:0] s;
+   assign result = s;
+
+  wire [1:0] __s_out;
+  always @* s[3:2] = __s_out;
+  SubModule sub(
+    .in(a),
+    .out(__s_out)
+  );
+
+   always @* begin
+        s[1:0] = b;
+   end
+
+endmodule
+
+module SubModule(
+  input wire [1:0] in,
+  output wire [1:0] out
+);
+
+  assign out = in;
+
+endmodule
\ No newline at end of file

test/relong/module_struct_tb.v

+`default_nettype none
+
+module top;
+
+    reg [4:0] __input;
+    wire [3:0] result;
+
+    Example dut(
+        .a(__input[3:2]),
+        .b(__input[1:0]),
+        .result(result)
+    );
+
+
+    initial begin
+        $monitor($time, "i: %b result: %b", __input, result);
+        for (__input = 0; __input < 5'hf; __input = __input + 1) begin
+            #10;
+        end
+        $finish;
+    end
+
+
+endmodule
\ No newline at end of file

test/relong/split_struct.sv

+`default_nettype none
+
+typedef struct packed {
+    logic [1:0] last;
+    logic [1:0] first;
+} MyStruct_t;
+
+
+module Example(
+    input logic [1:0] a, b,
+    output logic [3:0] result
+);
+
+   MyStruct_t s;
+   assign result = s;
+
+   assign s.last = a;
+   always_comb begin
+        s.first = b;
+   end
+
+endmodule
\ No newline at end of file

test/relong/split_struct.v

+`default_nettype none
+
+// typedef struct packed {
+//     logic [1:0] last;
+//     logic [1:0] first;
+// } MyStruct_t;
+
+
+module Example(
+    input wire [1:0] a, b,
+    output wire [3:0] result
+);
+
+   reg [3:0] s;
+   assign result = s;
+
+   // Convert to always @* block
+   // It might be easier to go directly to always @*
+   wire [1:0] _s_3_2;
+   assign _s_3_2[1:0] = a;
+   always @* s[3:2] = _s_3_2;
+
+   always @* begin
+        s[1:0] = b;
+   end
+
+endmodule
\ No newline at end of file

test/relong/split_struct_tb.v

+`default_nettype none
+
+module top;
+
+    reg [4:0] __input;
+    wire [3:0] result;
+
+    Example dut(
+        .a(__input[3:2]),
+        .b(__input[1:0]),
+        .result(result)
+    );
+
+
+    initial begin
+        $monitor($time, "i: %b result: %b", __input, result);
+        for (__input = 0; __input < 5'hf; __input = __input + 1) begin
+            #10;
+        end
+        $finish;
+    end
+
+
+endmodule
\ No newline at end of file