Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
S
sv2v
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
sv2v
Commits
767b05cd
Commit
767b05cd
authored
Feb 10, 2019
by
Zachary Snow
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
arguably cleaner Show output for AST modules
parent
14ba5dae
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
15 additions
and
16 deletions
+15
-16
Language/SystemVerilog/AST.hs
+15
-16
No files found.
Language/SystemVerilog/AST.hs
View file @
767b05cd
...
@@ -40,12 +40,16 @@ data Module
...
@@ -40,12 +40,16 @@ data Module
deriving
Eq
deriving
Eq
instance
Show
Module
where
instance
Show
Module
where
showList
modules
_
=
intercalate
"
\n
\n
"
$
map
show
modules
showList
modules
_
=
intercalate
"
\n
"
$
map
show
modules
show
(
Module
name
ports
items
)
=
unlines
show
(
Module
name
ports
items
)
=
unlines
[
"module "
++
name
++
(
if
null
ports
then
""
else
"("
++
commas
ports
++
")"
)
++
";"
[
"module "
++
name
++
portsStr
++
";"
,
unlines'
$
map
show
items
,
indent
$
unlines'
$
map
show
items
,
"endmodule"
,
"endmodule"
]
]
where
portsStr
=
if
null
ports
then
""
else
indentedParenList
ports
data
Direction
data
Direction
=
Input
=
Input
...
@@ -74,11 +78,6 @@ data ModuleItem
...
@@ -74,11 +78,6 @@ data ModuleItem
|
Localparam
(
Maybe
Range
)
Identifier
Expr
|
Localparam
(
Maybe
Range
)
Identifier
Expr
|
PortDecl
Direction
(
Maybe
Range
)
Identifier
|
PortDecl
Direction
(
Maybe
Range
)
Identifier
|
LocalNet
Type
Identifier
(
Maybe
Expr
)
|
LocalNet
Type
Identifier
(
Maybe
Expr
)
-- | Input (Maybe Range) [Identifier]
-- | Output (Maybe Range) [Identifier]
-- | Inout (Maybe Range) [Identifier]
-- | Wire (Maybe Range) [(Identifier, Maybe $ Either Range Expr)]
-- | Reg (Maybe Range) [(Identifier, Maybe $ Either Range Expr)]
|
Integer
[
Identifier
]
|
Integer
[
Identifier
]
|
Initial
Stmt
|
Initial
Stmt
|
Always
(
Maybe
Sense
)
Stmt
|
Always
(
Maybe
Sense
)
Stmt
...
@@ -100,11 +99,6 @@ instance Show ModuleItem where
...
@@ -100,11 +99,6 @@ instance Show ModuleItem where
if
v
==
Nothing
if
v
==
Nothing
then
""
then
""
else
" = "
++
show
(
fromJust
v
)
else
" = "
++
show
(
fromJust
v
)
-- Input r a -> printf "input %s%s;" (showRange r) (commas a)
-- Output r a -> printf "output %s%s;" (showRange r) (commas a)
-- Inout r a -> printf "inout %s%s;" (showRange r) (commas a)
-- Wire r a -> printf "wire %s%s;" (showRange r) (commas [ a ++ showAssign r | (a, r) <- a ])
-- Reg r a -> printf "reg %s%s;" (showRange r) (commas [ a ++ showRange r | (a, r) <- a ])
Integer
a
->
printf
"integer %s;"
$
commas
a
Integer
a
->
printf
"integer %s;"
$
commas
a
Initial
a
->
printf
"initial
\n
%s"
$
indent
$
show
a
Initial
a
->
printf
"initial
\n
%s"
$
indent
$
show
a
Always
Nothing
b
->
printf
"always
\n
%s"
$
indent
$
show
b
Always
Nothing
b
->
printf
"always
\n
%s"
$
indent
$
show
b
...
@@ -115,7 +109,7 @@ instance Show ModuleItem where
...
@@ -115,7 +109,7 @@ instance Show ModuleItem where
|
otherwise
->
printf
"%s #%s %s %s;"
m
(
showPorts
showExprConst
params
)
i
(
showPorts
show
ports
)
|
otherwise
->
printf
"%s #%s %s %s;"
m
(
showPorts
showExprConst
params
)
i
(
showPorts
show
ports
)
where
where
showPorts
::
(
Expr
->
String
)
->
[(
Identifier
,
Maybe
Expr
)]
->
String
showPorts
::
(
Expr
->
String
)
->
[(
Identifier
,
Maybe
Expr
)]
->
String
showPorts
s
ports
=
printf
"(%s)"
$
commas
[
if
i
==
""
then
show
(
fromJust
arg
)
else
printf
".%s(%s)"
i
(
if
isJust
arg
then
s
$
fromJust
arg
else
""
)
|
(
i
,
arg
)
<-
ports
]
showPorts
s
ports
=
indentedParenList
[
if
i
==
""
then
show
(
fromJust
arg
)
else
printf
".%s(%s)"
i
(
if
isJust
arg
then
s
$
fromJust
arg
else
""
)
|
(
i
,
arg
)
<-
ports
]
showRange
::
Maybe
Range
->
String
showRange
::
Maybe
Range
->
String
showRange
Nothing
=
""
showRange
Nothing
=
""
...
@@ -348,3 +342,8 @@ instance Show Sense where
...
@@ -348,3 +342,8 @@ instance Show Sense where
type
Range
=
(
Expr
,
Expr
)
type
Range
=
(
Expr
,
Expr
)
indentedParenList
::
[
String
]
->
String
indentedParenList
[]
=
"()"
indentedParenList
[
x
]
=
"("
++
x
++
")"
indentedParenList
l
=
"(
\n
"
++
(
indent
$
intercalate
",
\n
"
l
)
++
"
\n
)"
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment