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lvzhengyang
sv2v
Commits
73f83112
Commit
73f83112
authored
Apr 19, 2019
by
Zachary Snow
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trim empty blocks; remove extra space in implicitly typed decls
parent
8298e83f
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2 changed files
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2 additions
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1 deletions
+2
-1
src/Convert/Traverse.hs
+1
-0
src/Language/SystemVerilog/AST/Decl.hs
+1
-1
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src/Convert/Traverse.hs
View file @
73f83112
...
...
@@ -201,6 +201,7 @@ traverseSinglyNestedStmtsM :: Monad m => MapperM m Stmt -> MapperM m Stmt
traverseSinglyNestedStmtsM
fullMapper
=
cs
where
cs
(
StmtAttr
a
stmt
)
=
fullMapper
stmt
>>=
return
.
StmtAttr
a
cs
(
Block
Nothing
[]
[]
)
=
return
Null
cs
(
Block
name
decls
stmts
)
=
mapM
fullMapper
stmts
>>=
return
.
Block
name
decls
cs
(
Case
u
kw
expr
cases
def
)
=
do
...
...
src/Language/SystemVerilog/AST/Decl.hs
View file @
73f83112
...
...
@@ -26,7 +26,7 @@ instance Show Decl where
showList
l
_
=
unlines'
$
map
show
l
show
(
Parameter
t
x
e
)
=
printf
"parameter %s%s = %s;"
(
showPad
t
)
x
(
show
e
)
show
(
Localparam
t
x
e
)
=
printf
"localparam %s%s = %s;"
(
showPad
t
)
x
(
show
e
)
show
(
Variable
d
t
x
a
me
)
=
printf
"%s%s
%s%s%s;"
(
showPad
d
)
(
show
t
)
x
(
showRanges
a
)
(
showAssignment
me
)
show
(
Variable
d
t
x
a
me
)
=
printf
"%s%s
%s%s%s;"
(
showPad
d
)
(
showPad
t
)
x
(
showRanges
a
)
(
showAssignment
me
)
data
Direction
=
Input
...
...
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