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lvzhengyang
sv2v
Commits
6b81f87a
Commit
6b81f87a
authored
Jun 29, 2020
by
Zachary Snow
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fix stale logs in test runner
parent
82d06b39
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2 changed files
with
6 additions
and
1 deletions
+6
-1
test/lib/functions.sh
+5
-0
test/relong/functions_tb.v
+1
-1
No files found.
test/lib/functions.sh
View file @
6b81f87a
...
@@ -118,6 +118,11 @@ simulateAndCompare() {
...
@@ -118,6 +118,11 @@ simulateAndCompare() {
assertTrue
"VCDs are different:
\n
$output
"
$?
assertTrue
"VCDs are different:
\n
$output
"
$?
output
=
`
diff
$ref_log
$gen_log
`
output
=
`
diff
$ref_log
$gen_log
`
assertTrue
"Simulation outputs differ:
\n
$output
"
$?
assertTrue
"Simulation outputs differ:
\n
$output
"
$?
rm
-f
$ref_vcd
rm
-f
$gen_vcd
rm
-f
$ref_log
rm
-f
$gen_log
}
}
runTest
()
{
runTest
()
{
...
...
test/relong/functions_tb.v
View file @
6b81f87a
...
@@ -23,7 +23,7 @@ module top;
...
@@ -23,7 +23,7 @@ module top;
end
end
initial
begin
initial
begin
$
monitor
($
time
,
" data: %h check: %b
checkData: %h"
,
dataIn
,
{
check1
,
check2
}
,
checkData
)
;
$
monitor
($
time
,
" data: %h check: %b
%b checkData: %h"
,
dataIn
,
check1
,
check2
,
checkData
)
;
clear
=
1'b1
;
clear
=
1'b1
;
dataIn
=
8'h0
;
dataIn
=
8'h0
;
repeat
(
3
)
@
(
posedge
clock
)
;
repeat
(
3
)
@
(
posedge
clock
)
;
...
...
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