updated README with acknowledgments

README.md

@@ -12,7 +12,8 @@ conversion already exist, they generally either rely on commercial tools, or are
 limited in scope.
 
 This project was originally developed to target [Yosys], and so allows for
-disabling the conversion of (passing through) those [SystemVerilog features which Yosys supports].
+disabling the conversion of (passing through) those [SystemVerilog features
+which Yosys supports].
 
 [Yosys]: http://www.clifford.at/yosys/
 [SystemVerilog features which Yosys supports]: https://github.com/YosysHQ/yosys#supported-features-from-systemverilog
@@ -38,7 +39,7 @@ We plan on releasing pre-built binaries in the future.
 
 ### Building from source
 
-You must have [Stack] installed to build sv2v.  Then you can:
+You must have [Stack] installed to build sv2v. Then you can:
 
 [Stack]: https://www.haskellstack.org/
 
@@ -58,8 +59,8 @@ running `stack install`, or copy over the executable manually.
 ## Usage
 
 sv2v takes in a list of files and prints the converted Verilog to `stdout`.
-Users may specify `include` search paths, define macros during preprocessing, and
-exclude some of the conversion.
+Users may specify `include` search paths, define macros during preprocessing,
+and exclude some of the conversions.
 
 Below is the current usage printout. This interface is subject to change.
 
@@ -88,7 +89,7 @@ If you find a bug or have a feature request, please create an issue. Preference
 will be given to issues which include examples or test cases.
 
 
-## SystemVerilog Front end
+## SystemVerilog Front End
 
 This project contains a preprocessor and lexer, a parser, and an abstract syntax
 tree representation for a subset of the SystemVerilog specification. The parser
@@ -104,6 +105,22 @@ front end if there is significant interest.
 The current test suite is limited. Tests can be run with `make test`.
 
 
+## Acknowledgements
+
+This project was originally forked from [Tom Hawkin's Verilog parser]. While the
+front end has changed substantially in adding SystemVerilog support, his project
+was as a great starting point.
+
+[Tom Hawkin's Verilog parser]: https://github.com/tomahawkins/verilog
+
+Reid Long was invaluable in developing this tool, providing significant tests
+and advice, and isolating many bugs. His projects can be found
+[here](https://bitbucket.org/ReidLong/).
+
+Edric Kusuma helped me with the ins and outs of SystemVerilog, with which I had
+no prior experience, and has also helped with test cases.
+
+
 ## License
 
 See the LICENSE file for copyright and licensing information.